This presentation is part of the 2015 IEDM short course "Emerging CMOS Technology at 5nm and Beyond"
This Tutorial lecture covers the following topics:
- Scaling limitation of Cu/low-k interconnects
- CNT and graphene
- Optical interconnects
- 3-D integration: bonding/TSV
This tutorial is part of a larger short course, in which the world's leading experts were invited to give us their vision on what's needed for future CMOS technology to scale to 5 nm and beyond. 5 nm is within a factor of ten of the atomic size, which demands a paradigm shift in many aspects of the technology: device type, process integration, interconnect, patterning, and manufacturability.
For device and material options, III-V MOSFETs, band-to-band tunnel FETs, nanowire FETs, and 2D semiconductors were considered, among other options. Their merits and challenges, with reference to today's state-of-the-art 14 nm FinFETs, will be discussed. For process integration, the focus is on scaling of fully depleted devices, FinFETs, high-mobility channel material, and SRAM cell. Opportunities include horizontal and vertical nanowires with 3D integration. Interconnects will face power dissipation, insufficient bandwidth, and signal latency problems. The question is how far can we push C/low-k to its physical limitation? And will alternative schemes, like carbon nanotubes, optical interconnects, and 3D interconnects meet the challenge? Patterning at 5 nm and beyond will be extremely demanding, requiring a multiplex of resolution enhancing techniques and extreme ultra-violet lithography whose status will be reviewed. Challenges on the resist and mask will also have to be met. Variability is the maker or breaker of CMOS manufacturing at 5 nm. Various sources of local, global, and time dependent variability will be examined. Design-technology co-optimization (DTCO) were discussed as one of the possible solutions. The short course concluded with a few thoughts from the organizer on the historical perspective.
Krishna Saraswat is Rickey/Nielsen Chair Professor of Electrical Engineering at Stanford University. He received Ph.D. from Stanford University in 1974 and B.E. from BITS, Pilani in 1968. He His research interests are in new and innovative materials, structures, and process technology of silicon, germanium and III-V devices and metal and optical interconnects for nanoelectronics, and high efficiency and low cost solar cells. Prof. Saraswat has supervised more than 80 doctoral students, 25 post doctoral scholars and has authored or co-authored 15 patents and over 750 technical papers, of which 10 have received Best Paper Award. He is a Life Fellow of the IEEE. He received the Thomas Callinan Award from The Electrochemical Society in 2000, the 2004 IEEE Andrew Grove, Inventor Recognition Award from MARCO/FCRP in 2007, the Technovisionary Award from the India Semiconductor Association in 2007 and the Semiconductor Industry Association Researcher of the Year Award in 2012. He is listed by ISI as one of the 250 Highly Cited Authors in his field.
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