This presentation is part of the 8th IEEE/ACM Workshop on Variability Modeling and Characterization (VMC) 2015.
It is difficult to control the geometry, doping, and thicknesses of small transistors. Moreover, nanoscale transistors degrade due to NBTI and HCI at vastly different rates. Fortunately, designers have learned to live with these static and dynamic variabilities and produce extraordinarily fast and power-efficient ICs despite these variations. The job unfortunately is not done: In this talk, I will discuss the emerging issue of self-heating as a source of run-time variability that IC design must grapple with in the future technology nodes.
Here is the back story. By early 2000s, many researchers would begin their talks with an iconic cartoon that superimposed the images of rocket nozzles and the Sun onto a plot of the increasing power dissipation of an IC. The community heard the message: the voltage-scaling kept power-dissipation at bay. Fast forward to 2015 – the tyranny of short channel effects at the sub 32 nm nodes has led to the development of FIGFET and ETSOI technologies, with gate-all-around III-V transistors in the horizon. The short channel effects are controlled, but at the expense of additional self-heating of the system. Stacks of materials (several of which are poor thermal conductors) now surround the very hot channel to make the bad situation worse. In this talk, I will discuss our mapping the self-heating in 3D in surround gate transistors and how self-heating redefines and conflates the traditional notions of performance, variability and reliability of ultrathin transistors and frontend and backend issues of a modern IC. This complex, correlated design challenge can only be dealt with new class of IC design and optimization approaches.
Cite this work
Researchers should cite this work as follows: