JFETlab: An Online Simulation Tool for Double Gate long channel Symmetrical Si and 4H-SiC JFETs

By Nikolaos Makris1; Matthias Bucher1; Farzan Jazaeri2

1. School of Electrical and Computer Engineering (ECE) of the Technical University of Crete (TUC) 2. EPFL

JFETlab is a simulation tool of static and dynamic electrical characteristics ( I-V, G-V, C-V ) of Si and 4H-SiC Junction Field Effect Transistors (JFETs) using temperature and channel concentration depedent material models.

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Version 1.2 - published on 07 Jun 2021

doi:10.21981/2JXY-BK35 cite this

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    GmUt/Ids vs Ids for Si and 4H-SiC JFETs Output characteristics for Si and 4H-SiC JFETs Transfer characteristics for different temperatures C-V characteristics for Si and 4H-SiC JFETs

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Tools

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Abstract

N. Makris1, M. Bucher1, F. Jazaeri2 and J.-M. Sallese2

1Technical University of Crete, 73100  Chania, Greece

2EPFL, 1015 Lausanne, Switzerland

JFETLab evaluates DC and CV characteristics of a DG symmetrical Junction FET (JFET). The model is physics based and relies only on the structural parameters of the JFET and the electrical constants of the semiconductor. It incorporates the long channel charge based equations introduced in [1]-[5] .
he model utilizes Drift-Diffusion transport to evaluate the current (and trans-conductances), and Ward-Dutton (WD) partitioning scheme for evaluating total node charges and trans-capacitances. The model is continuous from below to above threshold and from linear to saturation modes and conserves symmetry among source and drain. The model ensures charge conservation in transient simulation as a result of the modelling of total node charges. The model has been validated with TCAD simulations [1]-[5] and measured devices [3]. As shown in [5], the model is capable of addressing silicon (Si), Silicon Carbide (4H-SiC) and Gallium Nitride(GaN) devices. Currently, the tool incorporates energy gap, intrinsic concentration and low field mobility models for Si and 4H-SiC[6-8]. The tool is implemented in Octave.

The three tabs under the label "Parameters" provide the simulation options. The user chooses the device material (Si or SiC) in the "Material Properties" tab. In "Instance Parameters" tab, the user can change channel doping(Nch), gate doping(Na), channel thickness (Tch), channel length (L) and channel width (W). The "Simulation Parameters" tab contains the simulation temperature (T) and drain-source voltage(Vds) and gate-source voltage(Vgs) for which the transfer and output characteristics are simulated.

The tool generates:

  • Ids vs Vgs (Transfer Characteristics using linear and log y-axis).
  • Ids vs Vds (Output Characteristics).
  • GmUt/Ids vs Vgs
  • GmUt/Ids Vs Ids
  • Gm, Gms, Gmd vs Vgs
  • Gm, Gms, Gmd vs Vds
  • Cgg, Cgs, Cgd vs  Vgs
  • Cdg, Cds, Cdd vs  Vgs
  • Csg, Csd, Css vs Vgs
  • Cgg, Cgs, Cgd vs  Vds
  • Cdg, Cds, Cdd vs  Vds
  • Csg, Csd, Css vs Vds

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Electronics Laboratory

School of Electrical and Computer Engineering (ECE)

Technical University of Crete (TUC)

73100 Chania, Greece

www.electronics.tuc.gr

References

[1] N. Makris, F. Jazaeri, J. M. Sallese, R. K. Sharma and M. Bucher, "Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs—Part I: Drain Current and Transconductances," in IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2744-2750, July 2018. doi: 10.1109/TED.2018.2838101
[2] N. Makris, F. Jazaeri, J. M. Sallese and M. Bucher, "Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs—Part II: Total Charges and Transcapacitances," in IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2751-2756, July 2018. doi: 10.1109/TED.2018.2838090
[3] N. Makris, M. Bucher, F. Jazaeri and J. M. Sallese, "A Compact Model for Static and Dynamic Operation of Symmetric Double-Gate Junction FETs," in European Solid State Device Research Conference (ESSDERC), Dresden, Germany, September 3-6, 2018.
[4] N. Makris, M. Bucher, K. Zekentes, "High Temperature Modeling of SiC and GaN JFETs," in European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham, UK, September 2-6, 2018.
[5] N. Makris, M. Bucher, F. Jazaeri and J. Sallese, "CJM: A Compact Model for Double-Gate Junction FETs," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 1191-1199, 2019, doi: 10.1109/JEDS.2019.2944817.
[6] B. Van Zeghbroeck,"Prinsiples of Semiconductor Devices" 2011, link
[7] D. Stefanakis, K. Zekentes,"TCAD models of the temperature and doping dependence of the bandgap and low field carrier mobility in 4H-SiC", in Microelectronic Engineering, vol. 116, p. 65-71, 2014
[8] D. Stefanakis,"Development of silicon carbide (SiC) micro vertical transverse field effect transistors", Phd Thesis, 2018, link

 

Cite this work

Researchers should cite this work as follows:

  • Nikolaos Makris, Matthias Bucher, Farzan Jazaeri (2021), "JFETlab: An Online Simulation Tool for Double Gate long channel Symmetrical Si and 4H-SiC JFETs," https://nanohub.org/resources/jfetlab. (DOI: 10.21981/2JXY-BK35).

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Tags

  1. charge
  2. current
  3. CV curves
  4. double gate trasistor
  5. JFET
  6. junction
  7. nanoelectronics