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With continual technology scaling, the accurate and efficient modeling and simulation of interconnect effects have become problems of central importance. In order to accurately model the distributive effects of interconnects, it is necessary to divide a long wire into several segments, with each regarded as a lumped RLC element. In this tutorial, two fundamental problems in the modeling and analysis of VLSI interconnects will be covered: (i) capacitance extraction and (ii) simulation of interconnects with inductive coupling.
For capacitance extraction, one approach is to use a boundary element technique for solving the integral form of Laplace equations. Such an approach usually involves an iterative solver whose most expensive operation is matrix-vector multiply. The tutorial will include a fast multi-pole method that relies on a hierarchical data structure to perform matrix-vector multiply in linear time complexity.
The second part of the tutorial will introduce a fast simulation technique for inductively coupled interconnects based on the notion of wire-duplication. The technique exploits the sparsity resident in the inverse of a inductance matrix to construct a small-sized equivalent RLC circuit. The wire-duplication technique improves simulation efficiency significantly while preserving simulation accuracy.
Researchers should cite this work as follows:
Cheng-Kok Koh (2007), "Modeling and Analysis of VLSI Interconnects," https://nanohub.org/resources/2698.
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