Interconnect, Emerging Logic Switches and Processor Core Energy-Delay Optimization

By Chi-Shuen Lee1, Saurabh Vinayak Suryavanshi1, H.-S. Philip Wong1

1. Stanford University, Stanford, CA

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Researchers should cite this work as follows:

  • Chi-Shuen Lee; Saurabh Vinayak Suryavanshi; H.-S. Philip Wong (2017), "Interconnect, Emerging Logic Switches and Processor Core Energy-Delay Optimization," http://nanohub.org/resources/27371.

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Room 101X, Paul G. Allen Building, Stanford University, Stanford, CA