p-bits for Probabilistic Spin Logic (PSL)

By Supriyo Datta

Electrical and Computer Engineering, Purdue University, West Lafayette, IN

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Digital electronics is based on stable bits that can have one of two values, 0 and 1. At the other extreme we have quantum computing using using q-bits that can be in superposition states that are 0 and 1 at the same time. In our recent work we have introduced a concept that is intermediate between bits and q-bits, namely a probabilistic bit or a p-bit that fluctuates randomly between 0 and 1.


In this talk, we will argue that within MRAM technology the magnetic tunnel junctions (MTJ’s) that store bits, with minor modifications, can represent p-bits as well. These can be used to build p-circuits for (1) combinatorial optimization, (2) Bayesian inference, (3) invertible Boolean logic that not only provides the output for given inputs, but also all inputs consistent with a given output, (4) image recognition and other machine learning applications.



Bayesian Inference and Optimization
Invertible Boolean
Non-magnetic implementation
  • [5] A.Z.Pervaiz, L.A.Ghantasala, K.Y. Camsari and S.Datta, “Hardware Emulation of Stochastic p-bits for Invertible Logic,” Scientific Reports, 7, 10994 (2017).
  • [6] A.Z.Pervaiz, L.A.Ghantasala, B.M.Sutton and K.Y. Camsari “Weighted p-bits for FPGA implementation of probabilistic circuits,” arxiv.org/abs/1712.04166.
Embedded MRAM based implementation

Cite this work

Researchers should cite this work as follows:

  • Supriyo Datta (2018), "p-bits for Probabilistic Spin Logic (PSL)," http://nanohub.org/resources/28491.

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Purdue University, West Lafayette, IN