pbits for Probabilistic Spin Logic (PSL)
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Abstract
Digital electronics is based on stable bits that can have one of two values, 0 and 1. At the other extreme we have quantum computing using using qbits that can be in superposition states that are 0 and 1 at the same time. In our recent work we have introduced a concept that is intermediate between bits and qbits, namely a probabilistic bit or a pbit that fluctuates randomly between 0 and 1.
In this talk, we will argue that within MRAM technology the magnetic tunnel junctions (MTJ’s) that store bits, with minor modifications, can represent pbits as well. These can be used to build pcircuits for (1) combinatorial optimization, (2) Bayesian inference, (3) invertible Boolean logic that not only provides the output for given inputs, but also all inputs consistent with a given output, (4) image recognition and other machine learning applications.
References
 Bayesian Inference and Optimization

 [1] B.BehinAein, V.Diep and S.Datta “A Building Block for Hardware Belief Networks”, Scientific Reports, 6, 29893 (2016).
 [2] B.M. Sutton, K.Y. Camsari, B. BehinAein and S.Datta “Intrinsic optimization using stochastic nanomagnets” Scientific Reports, 7, 44370 (2017).
 Invertible Boolean

 [3] K.Y. Camsari, R.Faria, B.M.Sutton and S.Datta “Stochastic pbits for Invertible Boolean Logic” Phys. Rev. X, 3, 031014 (2017).
 [4] R. Faria, K.Y. Camsari and S. Datta ” Low Barrier Nanomagnets as pbits for Spin Logic” IEEE Magnetics Letters, 8, 4105305 (2017).
 Nonmagnetic implementation

 [5] A.Z.Pervaiz, L.A.Ghantasala, K.Y. Camsari and S.Datta, “Hardware Emulation of Stochastic pbits for Invertible Logic,” Scientific Reports, 7, 10994 (2017).
 [6] A.Z.Pervaiz, L.A.Ghantasala, B.M.Sutton and K.Y. Camsari “Weighted pbits for FPGA implementation of probabilistic circuits,” arxiv.org/abs/1712.04166.
 Embedded MRAM based implementation

 [7] K.Y. Camsari, S. Salahuddin and S.Datta “Implementing pBits with Embedded MTJ’s,” IEEE Electron Device Letters, 38, 1767 (2017).
 [8] O.Hassan, K.Y.Camsari and S.Datta ”Voltagedriven Building Block for Hardware Belief Networks,” arxiv.org/abs/1801.09026.
 [9] R.Faria, K.Y.Camsari and S.Datta ”Implementing Bayesian Networks with Embedded MRAM,” AIP Advances, 8, 045101.
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Purdue University, West Lafayette, IN