p-bits for Probabilistic Spin Logic (PSL)

By Supriyo Datta

Electrical and Computer Engineering, Purdue University, West Lafayette, IN

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Abstract

Digital electronics is based on stable bits that can have one of two values, 0 and 1. At the other extreme we have quantum computing using using q-bits that can be in superposition states that are 0 and 1 at the same time. In our recent work we have introduced a concept that is intermediate between bits and q-bits, namely a probabilistic bit or a p-bit that fluctuates randomly between 0 and 1.

 

pBits

 

TALKS

  • This talk provides a 50-minute introduction by Prof. Datta.

  • A 10-minute version of the same talk can be viewed here.

  • A one hour tutorial lecture by Dr. Kerem Camsari can be viewed here.


SLIDES FROM A RECENT TALK

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TWO RECENT HIGHLIGHTS

  • Emulating qubits using p-bits

K.Y. Camsari, S. Chowdhury and S.Datta “Scaled Quantum Circuits Emulated with Room Temperature p-Bits,” https://arxiv.org/abs/1810.07144

  • FPGA implementation of p-bits

A.Z.Pervaiz, L.A.Ghantasala, B.M.Sutton and K.Y. Camsari “Weighted p-bits for FPGA implementation of probabilistic circuits,” IEEE Transactions on Neural Networks and Learning Systemsarxiv.org/abs/1712.04166.

 

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Cite this work

Researchers should cite this work as follows:

  • Supriyo Datta (2018), "p-bits for Probabilistic Spin Logic (PSL)," http://nanohub.org/resources/28491.

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Location

Purdue University, West Lafayette, IN

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