p-bits for Probabilistic Spin Logic (PSL): A Brief Introduction

By Supriyo Datta

Electrical and Computer Engineering, Purdue University, West Lafayette, IN

Published on

Abstract

Digital electronics is based on stable bits that can have one of two values, 0 and 1. At the other extreme we have quantum computing using using q-bits that can be in superposition states that are 0 and 1 at the same time. In our recent work we have introduced a concept that is intermediate between bits and q-bits, namely a probabilistic bit or p-bit that fluctuates randomly between 0 and 1.

pBits

This talk provides a brief 10-minute introduction. A more detailed presentation can viewed here.

References

Bayesian Inference and Optimization
Invertible Boolean
Non-magnetic implementation
  • [5] A.Z.Pervaiz, L.A.Ghantasala, K.Y. Camsari and S.Datta, “Hardware Emulation of Stochastic p-bits for Invertible Logic,” Scientific Reports, 7, 10994 (2017).
  • [6] A.Z.Pervaiz, L.A.Ghantasala, B.M.Sutton and K.Y. Camsari “Weighted p-bits for FPGA implementation of probabilistic circuits,” arxiv.org/abs/1712.04166.
Embedded MRAM based implementation

Cite this work

Researchers should cite this work as follows:

  • Supriyo Datta (2018), "p-bits for Probabilistic Spin Logic (PSL): A Brief Introduction," http://nanohub.org/resources/28680.

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Time

Location

Purdue University, West Lafayette, IN