p-bits for Probabilistic Spin Logic (PSL): A Brief Introduction

By Supriyo Datta

Electrical and Computer Engineering, Purdue University, West Lafayette, IN

Published on

Abstract

Digital electronics is based on stable bits that can have one of two values, 0 and 1. At the other extreme we have quantum computing using using q-bits that can be in superposition states that are 0 and 1 at the same time. In our recent work we have introduced a concept that is intermediate between bits and q-bits, namely a probabilistic bit or p-bit that fluctuates randomly between 0 and 1.

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References

Bayesian Inference and Optimization
  • [1] B.Behin-Aein, V.Diep and S.Datta “A Building Block for Hardware Belief Networks”, Scientific Reports 6, 29893 (2016).
  • [2] B.M. Sutton, K.Y. Camsari, B. Behin-Aein and S.Datta “Intrinsic optimization using stochastic nanomagnets” Scientific Reports, 7, 44370 (2017).
Invertible Boolean
  • [3] K.Y. Camsari, R.Faria, B.M.Sutton and S.Datta “Stochastic p-bits for Invertible Boolean Logic” Phys. Rev. X, 3, 031014 (2017).
  • [4] R. Faria, K.Y. Camsari and S. Datta ” Low Barrier Nanomagnets as p-bits for Spin Logic” IEEE Magnetics Letters, 8, 4105305 (2017).
Non-magnetic implementation
  • [5] A.Z.Pervaiz, L.A.Ghantasala, K.Y. Camsari and S.Datta, “Hardware Emulation of Stochastic p-bits for Invertible Logic,” Scientific Reports, 7, 10994 (2017).
  • [6] A.Z.Pervaiz, L.A.Ghantasala, B.M.Sutton and K.Y. Camsari “Weighted p-bits for FPGA implementation of probabilistic circuits,” arxiv.org/abs/1712.04166.
Embedded MRAM based implementation
  • [7] K.Y. Camsari, S. Salahuddin and S.Datta “Implementing p-Bits with Embedded MTJ’s,” IEEE Electron Device Letters, 38, 1767 (2017).
  • [8] O.Hassan, K.Y.Camsari and S.Datta ”Voltage-driven Building Block for Hardware Belief Networks,” arxiv.org/abs/1801.09026.
  • [9] R.Faria, K.Y.Camsari and S.Datta ”Implementing Bayesian Networks with Embedded MRAM,” AIP Advances, 8, 045101.

Cite this work

Researchers should cite this work as follows:

  • Supriyo Datta (2018), "p-bits for Probabilistic Spin Logic (PSL): A Brief Introduction," http://nanohub.org/resources/28680.

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Location

Purdue University, West Lafayette, IN