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ThrEshold Logic Synthesizer (TELS) and Majority Logic Synthezier (MALS)

By Pallav Gupta

VIllanova University

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Abstract

TELS and MALS are threshold and majority/minority logic synthesis tools that were developed by Rui Zhang and Pallav Gupta under the supervision of Prof. Niraj K. Jha of Princeton University. Dr. Lin Zhong, of Rice University, was also a contributor.

Both of these tools have been integrated into SIS which is a Boolean logic synthesis and optimization tool for UC Berkeley.

Credits

Dr. Rui Zhang - Mentor Graphics
Dr. Pallav Gupta - Villanova University
Dr. Lin Zhong - Rice University
Dr. Niraj K. Jha - Princeton University

Sponsored by

National Science Foundation

References

R. Zhang, P. Gupta, and N. K. Jha, Majority and Minority Networks Synthesis with Application to QCA, SET, and TPL Based Nanotechnologies, IEEE Trans. Computer-Aided Design, vol. 26, no. 7, pp. 1233-1245, July 2007.

R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, Threshold Network Synthesis and Optimization and Its Application to Nanotechnologies, IEEE Trans. Computer-Aided Design, vol. 24, no. 1, pp. 107-118, Jan. 2005, (top 25 most downloaded paper of TCAD

R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, "Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies," in Proc. Design Automation & Test in Europe Conf., Feb. 2004, pp. 904-909.

R. Zhang, P. Gupta, and N. K. Jha, "Synthesis of Majority and Minority Networks and its Applications to QCA, TPL, and SET based Nanotechnologies," in Proc. Int. Conf. VLSI Design, Jan. 2005, pp. 229-234.

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Researchers should cite this work as follows:

  • Pallav Gupta (2007), "ThrEshold Logic Synthesizer (TELS) and Majority Logic Synthezier (MALS)," http://nanohub.org/resources/3353.

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