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Reed-Muller Reversible Logic Synthesis tool (aka RELOS) is a tool for the synthesis of reversible functions based on positive-polarity Reed-Muller expressions. The second release of RMRLS a.k.a. RELOS features reversible logic synthesis with SWAP, Fredkin, and Peres gates.


This work was done under the supervision of Professor Niraj K. Jha. The students involved were Abhinav Agrawal and Pallav Gupta for RMRLS 0.1, and James Donald developed RMRLS 0.2.

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J. Donald and N. K. Jha. "Reversible Logic Synthesis with Fredkin and Peres Gates." ACM Journal Emerging Technologies Computing Systems, 2008 (accepted for publication).

P. Gupta, A. Agrawal, and N. K. Jha. "An Algorithm for Synthesis of Reversible Logic Circuits." IEEE Trans. Computer-Aided Design, vol. 24, no. 1, Nov. 2006.

A. Agrawal and N. K. Jha, "Synthesis of Reversible Logic." Design Automation and Test in Europe Conf., Feb. 2004.

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Researchers should cite this work as follows:

  • James Donald; Pallav Gupta (2007), "RMRLS 0.2,"

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