Reed-Muller Reversible Logic Synthesizer (RMRLS) 0.2
Reed-Muller Reversible Logic Synthesis tool (a.k.a. RELOS) is a tool for the synthesis of reversible functions based on positive-polarity Reed-Muller expressions. The second release of RMRLS features reversible logic synthesis with SWAP, Fredkin, and Peres gates.
2. P. Gupta, A. Agrawal, and N. K. Jha. "An Algorithm for Synthesis of Reversible Logic Circuits." IEEE Trans. Computer-Aided Design, vol. 24, no. 1, Nov. 2006.
3. A. Agrawal and N. K. Jha, "Synthesis of Reversible Logic." Design Automation and Test in Europe Conf., Feb. 2004.
Researchers should cite this work as follows:
James Donald; Pallav Gupta (2008), "Reed-Muller Reversible Logic Synthesizer (RMRLS) 0.2," https://nanohub.org/resources/3775.