The CMOS-nano hybrid technology tries to utilize the advantages of both traditional CMOS and novel nanowire/nanotube structures, which will enhance IC performances in the near future and create breakthroughs in the long run. The CMOS-nano hybrid IC can be efficiently fabricated using the 3D integration approach. This talk will present the recent progress in designing and building such 3D hybrid ICs for FPGA and neuromorphic network applications.
Researchers should cite this work as follows:
EE 317, Purdue University, West Lafayette, IN