Over the past three decades, silicon MOS-based integrated circuits, such as microprocessors, have consistently delivered greater functionality at higher performance and lower cost per function. An empirical observation called Moore’s Law is commonly quoted to highlight the exponential rates of increase in circuit speed and integration density as MOS transistors have scaled down in channel length. As devices have gotten smaller, faster and cheaper, demand for higher device performance has increased because computer systems have grown more widespread and complex. The driving force for continued scaling is lowering the cost per function, as scaling leads to more functions per unit area of the chip. Sometime within the next five years, traditional CMOS technology is expected to reach limits of scaling. As channel lengths shrink below 35 nm, complex channel profiles are required to achieve desired threshold voltages and to alleviate the short-channel effects. To fabricate devices beyond current scaling limits, IC companies are simultaneously pushing the planar, bulk silicon CMOS design while exploring
alternative gate stack materials (high-k dielectrics and metal gates), band engineering methods (using strained Si or SiGe), alternative transistor structures (dual-gate structures, FinFETs, etc. ), and alternative materials for reduced heat dissipation.
In fact, the challenge in identifying suitable high-k dielectrics and metal gates for both PMOS and NMOS transistors has led to early adoption of alternative transistor designs. These include fully-depleted (FD) SOI devices, dual gate (DG) structures, and FinFETs. Note that FD-SOI devices show promise for high-performance CMOS, microprocessors and system-on-a-chip designs. In such ultra-thin-body (UTB)-SOI structures, control of short-channel effects (SCE) and threshold voltage (Vt) adjustment can be realized with little or no channel doping. The purpose of this research work is to investigate transport quantum and heating effects in dual-gate and FinFET device structures.
Developed over 40 years ago, the NEGF formalism only recently became numerically viable for modeling semiconductor devices. Even now, however, the direct application of the NEGF is not an option for the quantum transport problem in three-dimensional or even sufficiently “large” two-dimensional structures. Thus, the key to the successful application of the NEGF formalism to the quantum transport problem in semiconductor nanostructures is the numerical efficiency. The goal of this presentation is to present a NEGF method we have developed few years back that is numerically efficient and ready for engineering applications in 2D and 3D objects on the one hand, and rigorously quantum-mechanical on the other hand. We also present some very important results from the FinFET analysis, such as optimization of the device structure, process variation etc.
To investigate lattice heating within a Monte Carlo device simulation framework, we simultaneously solve the Boltzmann transport equation for the electrons, the 2D Poisson equation to get the self-consistent fields and the hydrodynamic equations for acoustic and optical phonons. The phonon temperature then determines the choice of the scattering table. The bottom of the buried oxide layer (BOX) is assumed to be isothermal boundary and the temperature at that boundary is set to 300K. Another isothermal contact is the gate and the gate temperature is varied between 300-600 K. It is important to note that it takes only 4-5 Gummel cycles to get convergence in the current up to the third digit. More details of the simulation procedure can be found in Ref. . We find that in dual gate devices there exists larger bottleneck between acoustic and optical phonons which causes about 4% more degradation in the current in this device structure when compared to the single gate structure. This is easily explainable with the fact that there are more carriers in the DG structure and the optical to acoustic phonon decay is not fast enough so that heating has more influence on the carrier drift velocity and, therefore, on-state current in dual-gate devices. In fact, we do observe degradation in the average carrier velocity in the dual-gate devices when compared to single FD SOI device structure. Note that the dual-gate structure is a structure of choice according to these investigations because even though there is 4% more current degradation, the magnitude of the on-current is 1.5-1.8 times larger. Thus, we can trade off slight increase in current degradation due to lattice heating for more current drive.
- G. E. Moore, Electronics 38, No. 8, April 19 (1965).
- K. Raleva, D. Vasileska and S. M. Goodnick, “Heating Effects in Nanodevices”, IEEE Trans. Electron Devices, in press.
Researchers should cite this work as follows:
EE 317, Purdue University, West Lafayette, IN