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Illinois ECE 498AL: Programming Massively Parallel Processors, Lecture 6: CUDA Memories - Part 2

By Wen-Mei W Hwu

University of Illinois at Urbana-Champaign

Published on

Abstract

CUDA Memories Part2

Topics:

  • Tiled Multiply
  • Breaking Md and Nd into Tiles
  • Tiled Matrix Multiplication Kernel
  • CUDA Code - Kernel Execution Configuration
  • First Order Size considerations in G80
  • G80 Shared Memory and Threading
  • Tiling Size Effects
  • Typical Structure of a CUDA Program

Credits

These lecture were breezed by Carl Pearson and Daniel Borup and then reviewed, edited ,and Uploaded by Omar Sobh.

Sponsored by

NCN@illinois

Cite this work

Researchers should cite this work as follows:

  • Wen-Mei W Hwu (2009), "Illinois ECE 498AL: Programming Massively Parallel Processors, Lecture 6: CUDA Memories - Part 2," http://nanohub.org/resources/7247.

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