Measurements of Interface Trap Density in MOS Capacitors Using AC Conductance Method
Faculty Advisor(s): Cooper
4-H SiC MOS capacitors have a broad interface state density located at approximately 2.9eV above the valence band edge. These states reduce mobility through carrier trapping which in turn affects the electrical performance of these devices. The ac conductance technique is used to measure interface trap density, DIT. In this method, the complex admittance of the device is measured as a function of frequency at a fixed bias in depletion. Then, using a small signal ac equivalent circuit, the interface state conductance GP(ω) is extracted from the measured admittance. The magnitude of the peak of the GP/ω versus ln(ω) curve, at each bias, gives the interface state density opposite the Fermi level at the bias. Currently, we are developing a model using the same theory that is used to calculate the GP/ω curve to analyze the effect of a rapidly varying DIT. Using the data thus obtained, the standard conductance technique can be used to analyze this G P/ω curve as if it were actually experimental data. This method will therefore act as a check to determine if the D IT values obtained experimentally are acceptable. Discrepancies between the theoretical and experimental values would thus indicate the need for more careful experimental procedures.
Researchers should cite this work as follows:
Benafsha Shahlori (2004), "Measurements of Interface Trap Density in MOS Capacitors Using AC Conductance Method," https://nanohub.org/resources/742.
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