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At the nanometer scale, quantum transport approaches that are based on a full 3D Poisson-Schroedinger solution like the nanowire Lab or the atomistically resolved Bandstructure Lab are needed to provide insight into transport(1).
However, for devices that are 10nm or larger, semi-classical approaches can provide some significant insight. For device domains 30nm or larger, quantum approaches as implemented in today’s simulators, may not contain enough physics of scattering and dephasing. Therefore, there are some advantages in using classical simulation approaches over quantum simulation approaches for certain classes of device regimes. Drift and diffusion simulations are significantly faster than quantum ballistic simulations and also fairly well fitted to experimental results(2)
PROPHET is a PDE (partial differential equation) solver for 1, 2, or 3 dimension. It is developed in Bell Laboratories as a process simulator(3). Because of its capability of adopting new simulation modules to the core solver, it is used in various semiconductor device simulation.
PADRE is also developed in Bell Laboratories and a device-oriented simulator for 2D/3D device with arbitrary geometry(3). It provides many useful plots for engineers and deep understanding of physics. Many options are provided with respect to the numerical methods and semiconductor device physics. The numerical methods in PADRE are extremely robust. It can include hot-carrier transport by solving energy balance equation. The velocity of carriers in the channel region is fitted to the Monte Carlo simulation results(4).
MuGFET is user-friendly graphical user interface for users to simulate finFET and nanowire-FET structure using either PROPHET or PADRE. It provides a lot of useful plots such as subthreshold, DIBL, on/off current ratio, etc.
Various examples in this simulator is compared to the experimental results(5-7) in the First Time User Guide.
The tool is supported by a First Time User Guide.
- Recent change(Version 1.1.2)
- Example for a triple gate FET added
- Memory problem for triple gate FET fixed
- Gaussian doping for triple gate removed due to errors
- Version 1.1.1
- Example results updated for the upgraded PADRE (v1.3)
- Constant mesh size generation for memory saving
- Version 1.1
- Energy balance equation option included to understand hot carrier effect on transport
- Input sequence is changed for user’s convenience (Device Type-Structure-Material-Environment-Simulator-Simulate)
- Gaussian doping profile upgraded to be more realistic
- Refined meshes
- Minor error fixed(sequence plot for one Vd in PADRE
(1) Saumitra R. Mehrotra, “A simulation study on silicon nanowire field effect transistors(FETs)”, thesis, 2007
(2) M. R. Pinto, “ULSI Technology Development By Predictive Simulation”, IEDM, 1993
(3) P. Lloyd et al., Technology CAD at AT&T” , Microelectronics Journal, 26(1995), 79-97
(4) M. R. Pinto et al., “Silicon MOS Transconductance Scaling into the Overshoot Regime”, IEEE Electron Device Letters, Vol 14, No.8, 1993
(5) X. Huang et al., “Sub 50-nm FinFET: PMOS” , IEDM ,1999
(6) Sung Dae Suk, et al.,“High Performance 5nm radius Twin Silicon Nanowire MOSFET(TSNWFET) : Fabrication on Bulk Si Wafer, Characteristics, and Reliability”, IEDM 2005, pp 717-720, Dec 2005
(7) Yang-Kyu Choi, et al., “Y.K.Choi et. al. IEEE Electron Device Letters, 2002”, IEDM, 2001
Researchers should cite this work as follows: