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a TCAD Lab

By Gerhard Klimeck1, Dragica Vasileska2

1. Purdue University 2. Arizona State University

An Assembly of TCAD tools for circuit, device, and process simulation

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Version 1.0.1 - published on 12 Jan 2010

doi:10.4231/D3PC2T83V cite this

This tool is closed source.

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See also

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Usage

World usage

Location of all "a TCAD Lab" Users Since Its Posting

Simulation Users

1,690

5 38 58 94 146 173 215 222 234 246 261 287 307 322 338 349 359 388 401 450 467 477 490 507 538 552 568 585 609 633 646 659 685 708 733 756 806 889 910 927 944 957 980 1,011 1,074 1,095 1,112 1,128 1,148 1,166 1,188 1,206 1,223 1,250 1,274 1,314 1,349 1,368 1,388 1,405 1,438 1,485 1,500 1,532 1,556 1,599 1,634 1,653 1,664 1,690

Users By Organization Type
Type Users
Educational - University 1,143 (67.51%)
Unidentified 359 (21.2%)
Industry 113 (6.67%)
National Lab 26 (1.54%)
Unemployed 22 (1.3%)
Government Agency 15 (0.89%)
Educational - Pre-College 13 (0.77%)
Military 2 (0.12%)
Users by Country of Residence
Country Users
us UNITED STATES 342 (32.26%)
in INDIA 312 (29.43%)
kr KOREA, REPUBLIC OF 150 (14.15%)
my MALAYSIA 84 (7.92%)
de GERMANY 42 (3.96%)
tw TAIWAN 41 (3.87%)
fr FRANCE 27 (2.55%)
bd BANGLADESH 26 (2.45%)
pk PAKISTAN 19 (1.79%)
jp JAPAN 17 (1.6%)

Simulation Runs

19,494

34 244 359 519 664 725 916 935 957 989 1019 1149 1265 1386 1468 1505 1543 1624 1663 1912 2069 2094 2121 2175 2231 2301 2333 2360 2420 2502 2533 2573 2621 2681 2740 2802 2940 3683 3821 3887 3939 3977 4132 4660 11005 11213 11709 11863 12135 12314 13127 13589 13704 13955 14075 14446 15031 15163 15284 15378 15618 16295 16512 16824 17003 17558 18669 19288 19398 19494
Overview
Average Total
Wall Clock Time 5.71 hours 3034.13 days
CPU time 2.07 minutes 18.34 days
Interaction Time 45.81 minutes 405.87 days

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