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a TCAD Lab

By Gerhard Klimeck1, Dragica Vasileska2

1. Purdue University 2. Arizona State University

An Assembly of TCAD tools for circuit, device, and process simulation

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Version 1.0.2 - published on 05 Nov 2014

doi:10.4231/D3HT2GC5Z cite this

This tool is closed source.

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Usage

World usage

Location of all "a TCAD Lab" Users Since Its Posting

Simulation Users

1,953

5 38 58 94 146 173 215 222 234 246 261 287 307 322 338 349 359 388 401 450 467 477 490 507 538 552 568 585 609 633 646 659 685 708 733 756 806 889 910 927 944 957 980 1,011 1,074 1,095 1,112 1,128 1,148 1,166 1,188 1,206 1,223 1,250 1,274 1,314 1,349 1,368 1,388 1,405 1,438 1,485 1,500 1,532 1,556 1,599 1,634 1,653 1,664 1,692 1,713 1,746 1,776 1,803 1,852 1,884 1,909 1,953

Users By Organization Type
Type Users
Educational - University 1,257 (64.26%)
Unidentified 493 (25.2%)
Industry 124 (6.34%)
National Lab 27 (1.38%)
Unemployed 25 (1.28%)
Government Agency 15 (0.77%)
Educational - Pre-College 13 (0.66%)
Military 2 (0.1%)
Users by Country of Residence
Country Users
us UNITED STATES 375 (32.13%)
in INDIA 361 (30.93%)
kr KOREA, REPUBLIC OF 158 (13.54%)
my MALAYSIA 86 (7.37%)
de GERMANY 45 (3.86%)
tw TAIWAN 41 (3.51%)
bd BANGLADESH 31 (2.66%)
fr FRANCE 29 (2.49%)
jp JAPAN 21 (1.8%)
pk PAKISTAN 20 (1.71%)

Simulation Runs

23,450

34 244 359 519 664 725 916 935 957 989 1019 1149 1265 1386 1468 1505 1543 1624 1663 1912 2069 2094 2121 2175 2231 2301 2333 2360 2420 2502 2533 2573 2621 2681 2740 2802 2940 3683 3821 3887 3939 3977 4132 4660 11005 11213 11709 11863 12135 12314 13127 13589 13704 13955 14075 14446 15031 15163 15284 15378 15618 16295 16512 16824 17003 17558 18669 19288 19398 19512 19682 20084 20856 21755 22302 22461 22701 23450
Overview
Average Total
Wall Clock Time 5.02 hours 3224.07 days
CPU time 1.99 minutes 21.25 days
Interaction Time 44.33 minutes 474.42 days

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