Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling

28 Mar 2012 | Courses | Contributor(s): Souvik Mahapatra

This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has …

http://nanohub.org/resources/13613

Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Fast and Ultra-fast Characterization Methods (Part 1 of 3)

28 Mar 2012 | Online Presentations | Contributor(s): Souvik Mahapatra

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http://nanohub.org/resources/13614

Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Predictive Modeling (Part 3 of 3)

28 Mar 2012 | Online Presentations | Contributor(s): Souvik Mahapatra

This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has …

http://nanohub.org/resources/13612

Negative Bias Temperature Instability (NBTI) in p-MOSFETs: The Impact of Gate Insulator Processes (Part 2 of 3)

28 Mar 2012 | Online Presentations | Contributor(s): Souvik Mahapatra

This presentation is part 2 on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has …

http://nanohub.org/resources/13611

Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling (2011)

11 May 2011 | Online Presentations | Contributor(s): Souvik Mahapatra

This is a presentation on Negative Bias Temperature Instability, or in short NBTI, observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years …

http://nanohub.org/resources/11249

NanoV: Nanowire-based VLSI Design

08 Sep 2010 | Downloads | Contributor(s): muzaffer simsir

In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have …

http://nanohub.org/resources/9629

ECE 612 Lecture 23: RF CMOS

02 Dec 2008 | Online Presentations | Contributor(s): Mark Lundstrom

Outline: 1) Introduction, 2) Small signal model, 3) Transconductance, 4) Self-gain, 5) Gain bandwidth product, 6) Unity power gain, 7) Noise, mismatch, linearity…, 8) Examples

http://nanohub.org/resources/5961

ECE 612 Lecture 22: CMOS Circuit Essentials

24 Nov 2008 | Online Presentations | Contributor(s): Mark Lundstrom

Outline: 1) The CMOS inverter, 2) Speed, 3) Power, 4) Circuit performance, 5) Metrics, 6) Limits. This lecture is an overview of CMOS circuits. For a more detailed presentation, the …

http://nanohub.org/resources/5927

ECE 612 Lecture 18B: CMOS Process Flow

18 Nov 2008 | Online Presentations | Contributor(s): Mark Lundstrom

For a basic, CMOS process flow for an STI (shallow trench isolation process), see: http://www.rit.edu/~lffeee/AdvCmos2003.pdf. This lecture is a condensed version of the more complete presentation …

http://nanohub.org/resources/5855

ECE 612 Lecture 18A: CMOS Process Steps

12 Nov 2008 | Online Presentations | Contributor(s): Mark Lundstrom

Outline: 1) Unit Process Operations, 2) Process Variations.

http://nanohub.org/resources/5788