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nMOSFET RF and noise model on standard 45nm SOI technology
01 Jan 2017 | Compact Models | Contributor(s):
By Yanfei Shen1, Saeed Mohammadi1
A compact scalable model suitable for predicting high frequency noise and nonlinear behavior of N-type Metal Oxide Semiconductor (NMOS) transistors is presented.
A Phase-Changing Oxide for PS Silicon Photonics
03 Nov 2016 | | Contributor(s):: Richard Haglund
Advanced CMOS Device Physics for 7 nm and Beyond
16 Dec 2015 | | Contributor(s):: Scott Thompson
This presentation is part of 2015 IEDM tutorials The industry march along Moore's Law continues and new semiconductor nodes at 7 and beyond will certainly happen. However, many device, material, and economical challenges remain. This tutorial will target understanding key device concepts for...
Emerging CMOS Technology at 5 nm and Beyond: Device Options and Trade-offs
14 Dec 2015 | | Contributor(s):: Mark Lundstrom, Xingshu Sun, Dimitri Antoniadis, Shaloo Rakheja
Device Options and Trade-offs
Green Light on Germanium
02 Nov 2015 | | Contributor(s):: peide ye
This talk will review recent progress as well as challenges on Ge research for future logic applications with emphasis on the breakthrough work at Purdue University on Ge nFET which leads to the demonstration of the world first Ge CMOS circuits on Si substrates. Ge device technology includes...
Negative Capacitance Ferroelectric Transistors: A Promising Steep Slope Device Candidate?
30 Oct 2015 | | Contributor(s):: Suman Datta
In this talk, we will review progress in non-perovskite ALD based ferroelectric dielectrics which have strong implication for VLSI compatible negative capacitance Ferroelectric FETs.
Device Options and Trade-offs for 5 nm CMOS Technology Seminar Series
05 Oct 2015 | | Contributor(s):: Mark Lundstrom
Today's CMOS technology is so-called 14-nm technology. 10 nm technology development is well underway, and 7 nm has begun. It will soon be time to select a technology for the 5 nm node. To help understand the device options, what each on promises, what the challenges and trade-offs are,...
Nanometer-Scale III-V Electronics: from Quantum-Well Planar MOSFETs to Vertical Nanowire MOSFETs
05 Oct 2015 | | Contributor(s):: Juses A. del Alamo
This talk will review recent progress as well as challenges confronting III-V electronics for future logic applications with emphasis on the presenter’s research activities at MIT.
Ivan C R nascimento
RF Solid-State Vibrating Transistors
15 Feb 2014 | | Contributor(s):: Dana Weinstein
In this talk, I will discuss the Resonant Body Transistor (RBT), which can be integrated into a standard CMOS process. The first hybrid RF MEMS-CMOS resonators in Si at the transistor level of IBM’s SOI CMOS process, without any post-processing or packaging will be described. ...
Computational and Experimental Study of Transport in Advanced Silicon Devices
28 Jun 2013 | | Contributor(s):: Farzin Assad
In this thesis, we study electron transport in advanced silicon devices by focusing on the two most important classes of devices: the bipolar junction transistor (BJT) and the MOSFET. In regards to the BJT, we will compare and assess the solutions of a physically detailed microscopic model to...
Carbon-Based Nanoswitch Logic
28 Mar 2013 | | Contributor(s):: Stephen A. Campbell
This talk discusses a rather surprising possibility: the use of carbon-based materials such as carbon nanotubes and grapheneto make nanomechanical switches with at least an order of magnitude lower power dissipation than the low power CMOS options and performance between the various CMOS...
Mohamed Tarek Ghoneim
Uniform Methodology of Benchmarking Beyond-CMOS Devices
31 Oct 2012 | | Contributor(s):: Dmitri Nikonov
Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the CMOS roadmap. Structure and operational principles of these devices are described.Theories used for benchmarking these devices are...
In Search of a Better MEMS-Switch: An Elementary theory of how nanostructured dielectrics may soften landing, increase travel range, and decrease energy dissipation
06 Jun 2012 | | Contributor(s):: Muhammad Alam
In this talk, I will discuss an elementary theory of the role of nanostructured electrodes in addressing some of the challenges from a fundamentally different perspective. The goal is to start a conversation regarding the viability of the approaches suggested and see if the perspective offered...
Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling
28 Mar 2012 | | Contributor(s):: Souvik Mahapatra
This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner SiON...
Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Fast and Ultra-fast Characterization Methods (Part 1 of 3)