Tags: CMOS

Resources (1-20 of 22)

  1. A Phase-Changing Oxide for PS Silicon Photonics

    03 Nov 2016 | | Contributor(s):: Richard Haglund

  2. Advanced CMOS Device Physics for 7 nm and Beyond

    16 Dec 2015 | | Contributor(s):: Scott Thompson

    This presentation is part of 2015 IEDM tutorials The industry march along Moore's Law continues and new semiconductor nodes at 7 and beyond will certainly happen. However, many device, material, and economical challenges remain. This tutorial will target understanding key device concepts for...

  3. Carbon-Based Nanoswitch Logic

    28 Mar 2013 | | Contributor(s):: Stephen A. Campbell

    This talk discusses a rather surprising possibility: the use of carbon-based materials such as carbon nanotubes and grapheneto make nanomechanical switches with at least an order of magnitude lower power dissipation than the low power CMOS options and performance between the various CMOS...

  4. Computational and Experimental Study of Transport in Advanced Silicon Devices

    28 Jun 2013 | | Contributor(s):: Farzin Assad

    In this thesis, we study electron transport in advanced silicon devices by focusing on the two most important classes of devices: the bipolar junction transistor (BJT) and the MOSFET. In regards to the BJT, we will compare and assess the solutions of a physically detailed microscopic model to...

  5. Device Options and Trade-offs for 5 nm CMOS Technology Seminar Series

    05 Oct 2015 | | Contributor(s):: Mark Lundstrom

    Today's CMOS technology is so-called 14-nm technology.  10 nm technology development is well underway, and 7 nm has begun. It will soon be time to select a technology for the 5 nm node. To help understand the device options, what each on promises, what the challenges and trade-offs are,...

  6. ECE 612 Lecture 18A: CMOS Process Steps

    12 Nov 2008 | | Contributor(s):: Mark Lundstrom

    Outline: 1) Unit Process Operations,2) Process Variations.

  7. ECE 612 Lecture 18B: CMOS Process Flow

    18 Nov 2008 | | Contributor(s):: Mark Lundstrom

    For a basic, CMOS process flow for an STI (shallow trench isolation process), see: http://www.rit.edu/~lffeee/AdvCmos2003.pdf.This lecture is a condensed version of the more complete presentation (listed above) by Dr. Fuller.

  8. ECE 612 Lecture 22: CMOS Circuit Essentials

    24 Nov 2008 | | Contributor(s):: Mark Lundstrom

    Outline: 1) The CMOS inverter,2) Speed,3) Power,4) Circuit performance,5) Metrics,6) Limits.This lecture is an overview of CMOS circuits. For a more detailed presentation, the following lectures from the Fall 2006 teaching of this course should be viewed:Lecture 24: CMOS Circuits, Part I (Fall...

  9. ECE 612 Lecture 23: RF CMOS

    02 Dec 2008 | | Contributor(s):: Mark Lundstrom

    Outline: 1) Introduction,2) Small signal model,3) Transconductance,4) Self-gain,5) Gain bandwidth product,6) Unity power gain,7) Noise, mismatch, linearity…,8) Examples

  10. Emerging CMOS Technology at 5 nm and Beyond: Device Options and Trade-offs

    14 Dec 2015 | | Contributor(s):: Mark Lundstrom, Xingshu Sun, Dimitri Antoniadis, Shaloo Rakheja

    Device Options and Trade-offs

  11. Green Light on Germanium

    02 Nov 2015 | | Contributor(s):: peide ye

    This talk will review recent progress as well as challenges on Ge research for future logic applications with emphasis on the breakthrough work at Purdue University on Ge nFET which leads to the demonstration of the world first Ge CMOS circuits on Si substrates. Ge device technology includes...

  12. In Search of a Better MEMS-Switch: An Elementary theory of how nanostructured dielectrics may soften landing, increase travel range, and decrease energy dissipation

    06 Jun 2012 | | Contributor(s):: Muhammad Alam

    In this talk, I will discuss an elementary theory of the role of nanostructured electrodes in addressing some of the challenges from a fundamentally different perspective. The goal is to start a conversation regarding the viability of the approaches suggested and see if the perspective offered...

  13. Nanometer-Scale III-V Electronics: from Quantum-Well Planar MOSFETs to Vertical Nanowire MOSFETs

    05 Oct 2015 | | Contributor(s):: Juses A. del Alamo

    This talk will review recent progress as well as challenges confronting III-V electronics for future logic applications with emphasis on the presenter’s research activities at MIT.

  14. NanoV: Nanowire-based VLSI Design

    08 Sep 2010 | | Contributor(s):: muzaffer simsir

    In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nanotechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design...

  15. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling

    28 Mar 2012 | | Contributor(s):: Souvik Mahapatra

    This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner SiON...

  16. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Characterization, Material/Process Dependence and Predictive Modeling (2011)

    11 May 2011 | | Contributor(s):: Souvik Mahapatra

    This is a presentation on Negative Bias Temperature Instability, or in short NBTI, observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to...

  17. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Fast and Ultra-fast Characterization Methods (Part 1 of 3)

    28 Mar 2012 | | Contributor(s):: Souvik Mahapatra

  18. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: Predictive Modeling (Part 3 of 3)

    28 Mar 2012 | | Contributor(s):: Souvik Mahapatra

    This is a presentation on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner SiON...

  19. Negative Bias Temperature Instability (NBTI) in p-MOSFETs: The Impact of Gate Insulator Processes (Part 2 of 3)

    28 Mar 2012 | | Contributor(s):: Souvik Mahapatra

    This presentation is part 2 on Negative Bias Temperature Instability (NBTI), observed in p channel MOSFET devices. Though NBTI has been discovered more than 40 years ago, in the last 10 years it has become a very important reliability concern as the industry moved from thicker SiO2 to thinner...

  20. Negative Capacitance Ferroelectric Transistors: A Promising Steep Slope Device Candidate?

    30 Oct 2015 | | Contributor(s):: Suman Datta

    In this talk, we will review progress in non-perovskite ALD based ferroelectric dielectrics which have strong implication for VLSI compatible negative capacitance Ferroelectric FETs.