Support

Support Options

Submit a Support Ticket

 
Home › Tags › CNTFETLab › Questions & Answers

Tags: CNTFETLab

Categories

Note: Results do not include pending, unpublished, and some private items.

Questions & Answers (1-3 of 3)

  1. i modeled CNTFET in “CNTFET Lab”, but it is showing “not converging at 100”. How can i rectify this?

    Closed | Responses: 0

    http://nanohub.org/answers/question/1262

  2. while running simulation “execute idle at…….”

    Closed | Responses: 0

    Hai, While running the CNTFET simulations with the CNTFETLab, I am getting the executing information as

    “execute Idle at UFlorida-HPC…….” for a long time…I want...

    http://nanohub.org/answers/question/506

  3. why the tool is not working for negetive gate and drain bias?

    Closed | Responses: 0

    I tried to simulate for the I~V curves of planar CNTFET with negative gate and drain bias (basically a p-type FET), but it shows some error message. As indicated by the simulator we can use a...

    http://nanohub.org/answers/question/509

  • Results 1 - 3 of 3
  • Start
  • 1
  • End

Get Help

Get Involved

Legal

nanoHUB.org, a resource for nanoscience and nanotechnology, is supported by the National Science Foundation and other funding agencies. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.