why the tool is not working for negetive gate and drain bias?

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I tried to simulate for the I~V curves of planar CNTFET with negative gate and drain bias (basically a p-type FET), but it shows some error message. As indicated by the simulator we can use a range …

https://nanohub.org/answers/question/509

while running simulation "execute idle at......."

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Hai, While running the CNTFET simulations with the CNTFETLab, I am getting the executing information as "execute Idle at UFlorida-HPC......." for a long time...I want to know whether the …

https://nanohub.org/answers/question/506