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1. 7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations

   23 Aug 2013 | Contributor(s):: Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy

   This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table model was generated using NEMO5 atomistic...

2. Help, Error with simulation

   Q&A|Open | Responses: 1

   Dears

   I tried to simulate an LNA using Virtual-Source Carbon Nanotube Field-Effect Transistor using HSPICE 2008,03 but it gave me this error " hsp-vacomp: Error:...

   https://nanohub.org/answers/question/1540

3. 

   Elmira Tavakkoli

   https://nanohub.org/members/196743

4. How to specify the type

   Q&A|Closed | Responses: 0

   Dear

    

   I do not know how to specify the FETtype when using the VSCNFET　model?

   Would you mind if I ask you to answer  this issue

   Thank you...

   https://nanohub.org/answers/question/1953