Tags: MOS

All Categories (21-39 of 39)

  1. Quantum and Thermal Effects in Nanoscale Devices

    18 Sep 2008 | | Contributor(s):: Dragica Vasileska

    To investigate lattice heating within a Monte Carlo device simulation framework, we simultaneously solve the Boltzmann transport equation for the electrons, the 2D Poisson equation to get the self-consistent fields and the hydrodynamic equations for acoustic and optical phonons. The phonon...

  2. ECE 612 Lecture 3: MOS Capacitors

    09 Sep 2008 | | Contributor(s):: Mark Lundstrom

    Outline: 1) Short review,2) Gate voltage / surface potential relation,3) The flatbandvoltage,4) MOS capacitance vs. voltage, 5) Gate voltage and inversion layer charge.

  3. ABACUS - Assembly of Basic Applications for Coordinated Understanding of Semiconductors

    16 Jul 2008 | | Contributor(s):: Xufeng Wang, Dragica Vasileska, Gerhard Klimeck

    One-stop-shop for teaching semiconductor device education

  4. MOSFET Exercise

    07 Jul 2008 | | Contributor(s):: Dragica Vasileska, Gerhard Klimeck

    With this exercise students are familiarized with the punchthrough effect, the series resistance at the source and drain region and the importance of impact ionization at high gate and drain bias conditions.www.eas.asu.edu/~vasileskNSF

  5. MOSfet Homework Assignment - Role of Dielectric Constant and Thickness

    31 Jan 2008 | | Contributor(s):: David K. Ferry

    Use the MOSfet tool on nanoHUB to simulate a n-channel MOSFET with the following parameters:Lsd=LG=45nm (each 15 nodes), oxide thickness of 1.2 nm (K=3.9, 5 nodes),poly-Si gate, junction depth of 10 nm (20 nodes), and all other parametersat their nominal preset values.Now, change K to 20, and...

  6. Semiconductor Device Education Material

    28 Jan 2008 | | Contributor(s):: Gerhard Klimeck

    This page has moved to "a Wiki page format" When we hear the words, semiconductor device, we may think first of the transistors in PCs or video game consoles, but transistors are the basic component in all of the electronic devices we use in our daily lives. Electronic systems are...

  7. Is there any free licence drift diffusion device simulator that supports MOS and bipolar devices

    Open | Responses: 1

    A sequel to this question is : Is Bambi simulator still available ??

    http://nanohub.org/answers/question/39

  8. New Dimension in Performance: Harnessing 3D Integration Technology

    29 Nov 2007 | | Contributor(s):: Kerry Bernstein

    Despite generation on generation of scaling, computer chips have remained essentially 2-dimensional. Improvements in on-chip wire delay, and in the total number of inputs and outputs has not been able to keep up with improvements to the transistor, and its getting harder and harder to hide it!...

  9. Introduction to nanoMOS

    02 Jul 2007 | | Contributor(s):: James K Fodor, Jing Guo

    This learning module introduces nanoHUB users to the nanoMOS simulator. A brief introduction to nanoMOS is presented, followed by voiced presentations featuring the simulator in action. Upon completion of this module, users should be able to use this simulator to gain valuable insight into the...

  10. Illinois Tools: MOCA

    28 Mar 2007 | | Contributor(s):: Mohamed Mohamed, Umberto Ravaioli, Nahil Sobh, derrick kearney, Kyeong-hyun Park

    2D Full-band Monte Carlo (MOCA) Simulation for SOI-Based Device Structures

  11. CGTB

    15 Jun 2006 | | Contributor(s):: Gang Li, yang xu, Narayan Aluru

    Compute the charge density distribution and potential variation inside a MOS structure by using a coarse-grained tight binding model

  12. MOSCap

    06 Apr 2006 | | Contributor(s):: Akira Matsudaira, Saumitra Raj Mehrotra, Shaikh S. Ahmed, Gerhard Klimeck, Dragica Vasileska

    Capacitance of a MOS device

  13. Modeling Single and Dual-Gate Capacitors using SCHRED

    31 Mar 2006 | | Contributor(s):: Dragica Vasileska

    SCHRED stands for self-consistent solver of the 1D Poisson and 1D effective mass Schrodinger equation as applied to modeling single gate or dual-gate capacitors. The program incorporates many features such as choice of degenerate and non-degenerate statistics for semiclassical charge...

  14. Schred

    30 Mar 2006 | | Contributor(s):: Dragica Vasileska, Shaikh S. Ahmed, Gokula Kannan, Matteo Mannino, Gerhard Klimeck, Mark Lundstrom, Akira Matsudaira, Junzhe Geng

    SCHRED simulation software calculates the envelope wavefunctions and the corresponding bound-state energies in a typical MOS, SOS and a typical SOI structure.

  15. New Frontiers in Nanocomputing

    03 Nov 2005 |

    Welcome to Frontiers in Nanocomputing, a seminar series that focuseson systems issues for nanoelectronics. Our topic was FundamentalLimits of Digital Computation. The questions to each speaker were: Whatare the fundamental limits? How close are we to those limits? Howrelevant are they to real...

  16. CMOS Nanotechnology

    07 Jul 2004 | | Contributor(s):: Mark Lundstrom

    In non-specialist language, this talk introduces CMOS technology used for modern electronics. Beginning with an explanation of "CMOS," the speaker relates basic system considerations of transistor design and identifies future challenges for CMOS electronics. Anyone with an elementary...

  17. Schred Source Code Download

    09 Mar 2005 | | Contributor(s):: Dragica Vasileska,

    Schred 2.0 calculates the envelope wavefunctions and the corresponding bound-state energies in a typical MOS (Metal-Oxide-Semiconductor) or SOS (Semiconductor-Oxide- Semiconductor) structure and a typical SOI structure by solving self-consistently the one-dimensional (1D) Poisson equation and...

  18. Digital Electronics: Fundamental Limits and Future Prospects

    20 Jan 2004 |

    I will review some old and some recent work on the fundamental (and not so fundamental) limits imposed by physics of electron devices on their density and power consumption.

  19. Nanoelectronic Scaling Tradeoffs: What does Physics Have to Say?

    23 Sep 2003 | | Contributor(s):: Victor Zhirnov

    Beyond CMOS, several completely new approaches to information-processing and data-storage technologies and architectures are emerging to address the timeframe beyond the current SIA International Technology Roadmap for Semiconductors (ITRS). A wide range of new ideas have been proposed for...