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The metal–oxide–semiconductor field-effect transistor is a device used for amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gate electrode can induce a conducting channel between the two other contacts called source and drain. The channel can be of n-typeor p-type, and is accordingly called an nMOSFET or a pMOSFET (also commonly nMOS, pMOS). It is by far the most common transistor in both digital and analog circuits, though the bipolar junction transistor was at one time much more common. More information on MOSFET can be found here.
Lecture 2: Elementary Theory of the Nanoscale MOSFET
out of 5 stars
08 Sep 2008 | | Contributor(s):: Mark Lundstrom
A very simple (actually overly simple) treatment of the nanoscale MOSFET. This lecture conveys the essence of the approach using only simple mathematics. It sets the stage for the subsequent lectures.
Lecture 4: Scattering in Nanoscale MOSFETs
No MOSFET is ever fully ballistic - there is always some carrier scattering. Scattering makes the problem complicated and requires detailed numerical simulations to treat properly. My objective in this lecture is to present a simple, physical picture that describes the essence of the problem and...
Lecture 5: Application to State-of-the-Art FETs
The previous lessons may seem a bit abstract and mathematical. To see how this all works, we examine measured data and show how the theory presented in the previous lessons help us understand the operation of modern FETs.
Introduction: Physics of Nanoscale MOSFETs
26 Aug 2008 | | Contributor(s):: Mark Lundstrom
2008 NCN@Purdue Summer School: Electronics from the Bottom Up
26 Aug 2008 | | Contributor(s):: Muhammad A. Alam, Supriyo Datta, Mark Lundstrom
Electronics from the Bottom Up is designed to promote the bottom-up perspective by beginning at the nanoscale, and working up to the micro and macroscale of devices and systems. For electronic devices, this means first understanding the smallest electronic device – a single molecule with two...
Physics of Nanoscale MOSFETs
Transistor scaling has pushed channel lengths to the nanometer regime where traditional approaches to MOSFET device physics are less and less suitable This short course describes a way of understanding MOSFETs that is much more suitable than traditional approaches when the channel lengths are of...
Lecture 1: Review of MOSFET Fundamentals
A quick review of the traditional theory of the MOSFET along with a review of key device performance metrics. A short discussion of the limits of the traditional (drift-diffusion) approach and the meaning of ballistic transport is also included.
ABACUS - Assembly of Basic Applications for Coordinated Understanding of Semiconductors
16 Jul 2008 | | Contributor(s):: Xufeng Wang, Dragica Vasileska, Gerhard Klimeck
One-stop-shop for teaching semiconductor device education
MOSFET - Theoretical Exercises
03 Aug 2008 | | Contributor(s):: Dragica Vasileska, Gerhard Klimeck
07 Jul 2008 | | Contributor(s):: Dragica Vasileska, Gerhard Klimeck
With this exercise students are familiarized with the punchthrough effect, the series resistance at the source and drain region and the importance of impact ionization at high gate and drain bias conditions.www.eas.asu.edu/~vasileskNSF
MOSfet Homework Assignment - Role of Dielectric Constant and Thickness
31 Jan 2008 | | Contributor(s):: David K. Ferry
Use the MOSfet tool on nanoHUB to simulate a n-channel MOSFET with the following parameters:Lsd=LG=45nm (each 15 nodes), oxide thickness of 1.2 nm (K=3.9, 5 nodes),poly-Si gate, junction depth of 10 nm (20 nodes), and all other parametersat their nominal preset values.Now, change K to 20, and...
Semiconductor Device Education Material
28 Jan 2008 | | Contributor(s):: Gerhard Klimeck
This page has moved to "a Wiki page format"When we hear the words, semiconductor device, we may think first of the transistors in PCs or video game consoles, but transistors are the basic component in all of the electronic devices we use in our daily lives. Electronic systems are built from...
Simulation of highly idealized, atomic scale MQCA logic circuits
15 Nov 2007 | | Contributor(s):: Dmitri Nikonov, George Bourianoff
Spintronics logic devices based on majority gates formed by atomic-level arrangements of spins in the crystal lattice is considered. The dynamics of switching is modeled by time-dependent solution of the density-matrix equation with relaxation. The devices are shown to satisfy requirements for...
Electronics From the Bottom Up: top-down/bottom-up views of length
17 Aug 2007 | | Contributor(s):: Muhammad A. Alam
When devices get small stochastic effects become important. Random dopant effects lead to uncertainties in a MOSFET’s threshold voltage and gate oxides breakdown is a random process. Even a concept as simple as “channel length” becomes uncertain. This short (20 min) talk, a footnote to the...
13 May 2004 | | Contributor(s):: Steven Clark
Introduction to nanoMOS
02 Jul 2007 | | Contributor(s):: James K Fodor, Jing Guo
This learning module introduces nanoHUB users to the nanoMOS simulator. A brief introduction to nanoMOS is presented, followed by voiced presentations featuring the simulator in action. Upon completion of this module, users should be able to use this simulator to gain valuable insight into the...
PETE : Purdue Emerging Technology Evaluator
26 Jun 2007 | | Contributor(s):: Arijit Raychowdhury, Charles Augustine, Yunfei Gao, Mark Lundstrom, Kaushik Roy
Estimate circuit level performance and power of novel devices
CMOS-Nano Hybrid Technology: a nanoFPGA-related study
04 Apr 2007 | | Contributor(s):: Wei Wang
Dr. Wei Wang received his PhD degree in 2002 from Concordia University, Montreal, QC, Canada, in Electrical and Computer Engineering. From 2002 to 2004, he was an assistant professor in the Department of Electrical and Computer Engineering, the University of Western Ontario, London, ON, Canada....
MSE 376 Lecture 13: Nanoscale CMOS, part 2
31 Mar 2007 | | Contributor(s)::
MSE 376 Lecture 12: Nanoscale CMOS, part 1