Tags: MOSFET

Description

The metal–oxide–semiconductor field-effect transistor is a device used for amplifying or switching electronic signals. In MOSFETs, a voltage on the oxide-insulated gate electrode can induce a conducting channel between the two other contacts called source and drain. The channel can be of n-typeor p-type, and is accordingly called an nMOSFET or a pMOSFET (also commonly nMOS, pMOS). It is by far the most common transistor in both digital and analog circuits, though the bipolar junction transistor was at one time much more common. More information on MOSFET can be found here.

All Categories (121-140 of 141)

  1. transfer characteristic

    Open | Responses: 2

    how the transfer characteristic of a mosfet depends on the channel doping?(theory)

    http://nanohub.org/answers/question/31

  2. Simulation of highly idealized, atomic scale MQCA logic circuits

    15 Nov 2007 | | Contributor(s):: Dmitri Nikonov, George Bourianoff

    Spintronics logic devices based on majority gates formed by atomic-level arrangements of spins in the crystal lattice is considered. The dynamics of switching is modeled by time-dependent solution of the density-matrix equation with relaxation. The devices are shown to satisfy requirements for...

  3. David Espejo

    Former grad student affiliated with the Microelectronics Center at "Universidad de los Andes" or University of the Andes, Bogota- Colombia.Current interests: HPC for nanoscale-devices...

    http://nanohub.org/members/23702

  4. Electronics From the Bottom Up: top-down/bottom-up views of length

    17 Aug 2007 | | Contributor(s):: Muhammad A. Alam

    When devices get small stochastic effects become important. Random dopant effects lead to uncertainties in a MOSFET’s threshold voltage and gate oxides breakdown is a random process. Even a concept as simple as “channel length” becomes uncertain. This short (20 min) talk, a footnote to the...

  5. Medici

    13 May 2004 | | Contributor(s):: Steven Clark

    MEDICI (Synopsys)

  6. Introduction to nanoMOS

    02 Jul 2007 | | Contributor(s):: James K Fodor, Jing Guo

    This learning module introduces nanoHUB users to the nanoMOS simulator. A brief introduction to nanoMOS is presented, followed by voiced presentations featuring the simulator in action. Upon completion of this module, users should be able to use this simulator to gain valuable insight into the...

  7. PETE : Purdue Emerging Technology Evaluator

    26 Jun 2007 | | Contributor(s):: Arijit Raychowdhury, Charles Augustine, Yunfei Gao, Mark Lundstrom, Kaushik Roy

    Estimate circuit level performance and power of novel devices

  8. CMOS-Nano Hybrid Technology: a nanoFPGA-related study

    04 Apr 2007 | | Contributor(s):: Wei Wang

    Dr. Wei Wang received his PhD degree in 2002 from Concordia University, Montreal, QC, Canada, in Electrical and Computer Engineering. From 2002 to 2004, he was an assistant professor in the Department of Electrical and Computer Engineering, the University of Western Ontario, London, ON, Canada....

  9. MSE 376 Lecture 13: Nanoscale CMOS, part 2

    31 Mar 2007 |

  10. MSE 376 Lecture 12: Nanoscale CMOS, part 1

    31 Mar 2007 |

  11. Illinois Tools: MOCA

    28 Mar 2007 | | Contributor(s):: Mohamed Mohamed, Umberto Ravaioli, Nahil Sobh, derrick kearney, Kyeong-hyun Park

    2D Full-band Monte Carlo (MOCA) Simulation for SOI-Based Device Structures

  12. MOSCNT: code for carbon nanotube transistor simulation

    14 Nov 2006 | | Contributor(s):: Siyu Koswatta, Jing Guo, Dmitri Nikonov

    Ballistic transport in carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) is simulated using the Non-equilibrium Green’s function formalism. A cylindrical transistor geometry with wrapped-around gate and doped source/drain regions are assumed. It should be noted...

  13. Nanoscale MOSFETs: Physics, Simulation and Design

    26 Oct 2006 |

    This thesis discusses device physics, modeling and design issues of nanoscale transistors at the quantum level. The principle topics addressed in this report are 1) an implementation of appropriate physics and methodology in device modeling, 2) development of a new TCAD (technology computer...

  14. nanoMOS 2.0: A Two -Dimensional Simulator for Quantum Transport in Double-Gate MOSFETs

    06 Oct 2006 | | Contributor(s):: Zhibin Ren, Ramesh Venugopal, Sebastien Goasguen, Supriyo Datta, Mark Lundstrom

    A program to numerically simulate quantum transport in double gate MOSFETs is described. The program uses a Green’s function approach and a simple treatment of scattering based on the idea of so-called Büttiker probes. The double gate device geometry permits an efficient mode space approach that...

  15. Modeling Interface-defect Generation (MIG)

    18 Jul 2006 | | Contributor(s):: Ahmad Ehteshamul Islam, HALDUN KUFLUOGLU, Muhammad A. Alam

    Analyzes device reliability based on NBTI

  16. MOSFet

    30 Mar 2006 | | Contributor(s):: Shaikh S. Ahmed, Saumitra Raj Mehrotra, SungGeun Kim, Matteo Mannino, Gerhard Klimeck, Dragica Vasileska, Xufeng Wang, Himadri Pal, Gloria Wahyu Budiman

    Simulates the current-voltage characteristics for bulk, SOI, and double-gate Field Effect Transistors (FETs)

  17. Saumitra Raj Mehrotra

    Saumitra finished his PhD from Purdue University  (Prof. Gerhard Klimeck) in 2014. He received his MS degree in May 2007 from University of Cincinnati working with Prof. K.P....

    http://nanohub.org/members/10858

  18. Fabrication of a MOSFET within a Microprocessor

    16 Nov 2005 |

    This resource depicts the step-by-step process by which the transistors of an integrated circuit are made.

  19. FETToy 2.0 Source Code Download

    09 Mar 2005 |

    FETToy 2.0 is a set of Matlab scripts that calculate the ballistic I-V characteristics for a conventional MOSFETs, Nanowire MOSFETs and Carbon NanoTube MOSFETs. For conventional MOSFETs, FETToy assumes either a single or double gate geometry and for a nanowire and nanotube MOSFETs it assumes a...

  20. Faster Materials versus Nanoscaled Si and SiGe: A Fork in the Roadmap?

    20 Apr 2004 | | Contributor(s):: Jerry M. Woodall

    Strained Si and SiGe MOSFET technologies face fundamental limits towards the end of this decade when the technology roadmap calls for gate dimensions of 45 nm headed for 22 nm. This fact, and difficulties in developing a suitable high-K dielectric, have stimulated the search for alternatives to...