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Progress in technology has brought microelectronics to the nanoscale, but nanoelectronics is not yet a well-defined engineering discipline with a coherent, experimentally verified, theoretical framework. The NCN has a vision for a new, 'bottom-up' approach to electronics, which involves: understanding electronic conduction at the atomistic level; formulating new simulation techniques; developing a new generation of software tools; and bringing this new understanding and perspective into the classroom. We address problems in atomistic phenomena, quantum transport, percolative transport in inhomogeneous media, reliability, and the connection of nanoelectronics to new problems such as biology, medicine, and energy. We work closely with experimentalists to understand nanoscale phenomena and to explore new device concepts. In the course of this work, we produce open source software tools and educational resources that we share with the community through the nanoHUB.
This page is a starting point for nanoHUB users interested in nanoelectronics. It lists key resources developed by the NCN Nanoelectronics team. The nanoHUB contains many more resources for nanoelectronics, and they can be located with the nanoHUB search function. To find all nanoelectronics resources, search for 'nanoelectronics.' To find those contributed by the NCN nanoelectronics team, search for 'NCNnanoelectronics.'
More information on Nanoelectronics can be found here.
ECE 659 Lecture 3: The Quantum of Conductance
out of 5 stars
17 Jan 2003 | | Contributor(s):: Supriyo Datta
Reference Chapter 1.3
Exploring New Channel Materials for Nanoscale CMOS
21 May 2006 | | Contributor(s):: anisur rahman
The improved transport properties of new channel materials, such as Ge and III-V semiconductors, along with new device designs, such as dual gate, tri gate or FinFETs, are expected to enhance the performance of nanoscale CMOS devices.Novel process techniques, such as ALD, high-k dielectrics, and...
Device Physics and Simulation of Silicon Nanowire Transistors
20 May 2006 |
As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention from both the semiconductor industry...
19 May 2006 | | Contributor(s):: Hong-Hyun Park, Lang Zeng, Matthew Buresh, Siqi Wang, Gerhard Klimeck, Saumitra Raj Mehrotra, Clemens Heitzinger, Benjamin P Haley
Simulate 3D nanowire transport in the effective mass approximation with phonon scattering and 3D Poisson self-consistent solution
Band Structure Lab
19 May 2006 | | Contributor(s):: Samik Mukherjee, Kai Miao, Abhijeet Paul, Neophytos Neophytou, Raseong Kim, Junzhe Geng, Michael Povolotskyi, Tillmann Christoph Kubis, Arvind Ajoy, Bozidar Novakovic, James Fonseca, Hesameddin Ilatikhameneh, Sebastian Steiger, Michael McLennan, Mark Lundstrom, Gerhard Klimeck
Computes the electronic and phonon structure of various materials in the spatial configuration of bulk , quantum wells, and wires
ECE 659 Lecture 1: Energy Level Diagram
16 May 2006 | | Contributor(s):: Supriyo Datta
Switching Energy in CMOS Logic: How far are we from physical limit?
24 Apr 2006 | | Contributor(s):: Saibal Mukhopadhyay
Aggressive scaling of CMOS devices in technology generation has resulted in exponential growth in device performance, integration density and computing power. However, the power dissipated by a silicon chip is also increasing in every generation and emerging as a major bottleneck to technology...
Nanoscale Transistors: Advanced VLSI Devices (Introductory Lecture)
20 Apr 2006 | | Contributor(s):: Mark Lundstrom
Welcome to the ECE 612 Introductory/Overview lecture. This course examines the device physics of advanced transistors and the process, device, circuit, and systems considerations that enter into the development of new integrated circuit technologies.
11 Apr 2006 |
Nanotechnology comprises the techniques for making things small (<100 nm) — i.e., nanopatterning — and the resulting applications, ranging from the results of undirected nanopatterning such as Goretex, paint, and reactive gold nanoparticles, to those of directed nanopatterning such as...
06 Apr 2006 | | Contributor(s):: Akira Matsudaira, Saumitra Raj Mehrotra, Shaikh S. Ahmed, Gerhard Klimeck, Dragica Vasileska
Capacitance of a MOS device
Modeling Single and Dual-Gate Capacitors using SCHRED
31 Mar 2006 | | Contributor(s):: Dragica Vasileska
SCHRED stands for self-consistent solver of the 1D Poisson and 1D effective mass Schrodinger equation as applied to modeling single gate or dual-gate capacitors. The program incorporates many features such as choice of degenerate and non-degenerate statistics for semiclassical charge...
30 Mar 2006 | | Contributor(s):: Shaikh S. Ahmed, Saumitra Raj Mehrotra, SungGeun Kim, Matteo Mannino, Gerhard Klimeck, Dragica Vasileska, Xufeng Wang, Himadri Pal, Gloria Wahyu Budiman
Simulates the current-voltage characteristics for bulk, SOI, and double-gate Field Effect Transistors (FETs)
Metal Oxide Nanowires: Synthesis, Characterization and Device Applications
07 Mar 2006 | | Contributor(s):: Jia Grace Lu
Various metal oxide nanowires, such as ZnO, SnO2, Fe2O3, In2O3 and Ga2O3, have been synthesized by chemical vapor deposition method. Their structures and properties are characterized by TEM, SEM, XRD, AFM, photoluminescence, photoconductance, scanning surface potential microscopy, and electrical...
14 Feb 2006 | | Contributor(s):: Baudilio Tejerina
Quantum Chemsitry Lab: Ab Initio and DFT molecular and electronic structure calculations of small molecules
Molecular Transport Structures: Elastic Scattering, Vibronic Effects and Beyond
13 Feb 2006 | | Contributor(s):: Mark Ratner, Abraham Nitzan,
Current experimental efforts are clarifying quite beautifully the nature of charge transport in so-called molecular junctions, in which a single molecule provides the channel for current flow between two electrodes. The theoretical modeling of such structures is challenging, because of the...
Making the Tiniest and Fastest Transistor using Atomic Layer Deposition (ALD)
13 Feb 2006 | | Contributor(s):: peide ye
Atomic layer deposition (ALD) is an emerging nanotechnology enables the deposit of ultrathin films, one atomic layer by one atomic layer. ALD provides a powerful, new capability to grow or regrow nanoscale ultrathin films of metals, semiconductors and insulators. This presentation introduces ALD...
30 Mar 2006 | | Contributor(s):: Dragica Vasileska, Shaikh S. Ahmed, Gokula Kannan, Matteo Mannino, Gerhard Klimeck, Mark Lundstrom, Akira Matsudaira, Junzhe Geng
SCHRED simulation software calculates the envelope wavefunctions and the corresponding bound-state energies in a typical MOS, SOS and a typical SOI structure.
Quantum-dot Cellular Automata (QCA) - Memory Cells
03 Feb 2006 |
Scientists and engineers are looking for completely different ways of storing and analyzing information. Quantum-dot Cellular Automata are one possible solution. In computers of the future, transistors may be replaced by assemblies of quantum dots called Quantum-dot Cellular Automata (QCAs).This...
Quantum-dot Cellular Automata (QCA) - Logic Gates
An earlier animation described how "Quantum-dot Cellular Automata" (QCAs) could serve as memory cells and wires. This animation contnues the story by describing how QCAs can be made into MAJORITY, OR, AND, and INVERTER logic gates.
A Primer on Semiconductor Device Simulation
23 Jan 2006 | | Contributor(s):: Mark Lundstrom
Computer simulation is now an essential tool for the research and development of semiconductor processes and devices, but to use a simulation tool intelligently, one must know what's "under the hood." This talk is a tutorial introduction designed for someone using semiconductor device simulation...