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FDNS21: Disorder and Defects in van der Waals Heterostructures
11 May 2021 | | Contributor(s):: Daniel A Rhodes
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FDNS21: Realizing 2D Transport in 2D Van der Waals Crystals
27 Apr 2021 | | Contributor(s):: Jiwoong Park
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FDNS21: Artificial van der Waals Crystals
27 Apr 2021 | | Contributor(s):: Cheol-Joo Kim
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nanoHUB MuGFET Tool Tutorial
05 Mar 2021 | | Contributor(s):: Ashish anil Bait
This is a basic tutorial on how to use the nanohub MuGFET tool to simulate FinFET or double gate model free of cost.
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Short Channel Effects
05 Mar 2021 | | Contributor(s):: Ashish anil Bait
Here are the all short channel effects that you require.
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Concept of FinFET Part-I
05 Mar 2021 | | Contributor(s):: Ashish anil Bait
Here is the video introducing latest transistor technology used in processors.
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Concept of FinFET Part-II
05 Mar 2021 | | Contributor(s):: Ashish anil Bait
Here is the video introducing latest transistor technology used in processors.
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Short Course on FinFET Simulation using MuGFET
05 Mar 2021 | | Contributor(s):: Ashish anil Bait
This short course present how to use nanohub MuGFET tool to simulate FinFET or double gate model. It provides a short background on FinFET followed by instructions on how to use the MuGFET tool for the FinFET simulation.
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MIT Atomic-Scale Modeling Toolkit
15 Jan 2008 | | Contributor(s):: David Strubbe, Enrique Guerrero, daniel richards, Elif Ertekin, Jeffrey C Grossman, Justin Riley
Tools for Atomic-Scale Modeling
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2DFET
18 Feb 2021 | | Contributor(s):: Ning Yang, Tong Wu, Jing Guo
Calculate the I-V characteristics of field-effect transistors (FETs) based on monolayer two-dimensional (2D) materials.
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DFT Results Explorer
04 Oct 2020 | | Contributor(s):: Saaketh Desai, Juan Carlos Verduzco Gastelum, Daniel Mejia, Alejandro Strachan
Use visualization tools to explore correlations in a DFT simulation results database
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Recursive algorithm for NEGF in Python GPU version
02 Feb 2021 | | Contributor(s):: Ning Yang, Tong Wu, Jing Guo
This folder contains two Python functions for GPU-accelerated simulation, which implements the recursive algorithm in the non-equilibrium Green’s function (NEGF) formalism. Compared to the matlab implementation [1], the GPU version allows massive parallel running over many cores on GPU...
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pntoy using simtool infrastructure
02 Feb 2021 | | Contributor(s):: Daniel Mejia
PNJunction Simtool
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Heat Transfer Quiz 1
01 Feb 2021 | | Contributor(s):: Kunal Dixit
Diagnostic Heat Transfer Quiz 1
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MOSFET Design
12 Jan 2021 | | Contributor(s):: Stella Quinones, Jose Valdez
A series of homework assignments were created to introduce senior level undergraduate Electrical and Computer Engineering students to the design of MOSFETs by combining calculations of MOSFET related design parameters for a set of doping and oxide thickness values with the analysis of MOSFET...
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Thermal Conductivity Simulator
03 Dec 2020 | | Contributor(s):: Md Shajedul Hoque Thakur, Md Mahbubul Islam
Simulate thermal conductivity of Silicon using reverse non-equilibrium molecular dynamics simulations.
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Compact NEGF-Based Solver for Double-Gate MOSFETs
17 Nov 2020 | | Contributor(s):: Fabian Hosenfeld, Alexander Kloes
Fast simulation of the DC current in a nanoscale double-gate MOSFET including thermionic emission and source-to-drain tunneling current.
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A Single Atom Transistor: The Ultimate Scaling Limit – Entry into Quantum Computing
14 Oct 2020 | | Contributor(s):: Gerhard Klimeck
50th European Solid-State Device Research Conference
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09 Demonstration of Vertical GaN PN Diode with Step-etched Triple zone JTE
14 Oct 2020 | | Contributor(s):: Hyun-Soo Lee, Yuxuan Zhang, Zhaoying Chen, Mohammad Wahidur Rahman, Hongping Zhao, Siddharth Rajan
We have demonstrated significantly improved BV of vertical GaN PN diode with STJTE without any degradation of forward characteristics. This is the first demonstration of a step-etched multiple zone edge termination for III-Nitride technology.
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25 Linearity by Synthesis: An Intrinsically Linear AlGaN/GaN-on-Si Transistor with OIP3/(F-1)PDC of 10.1 at 30 GHz
21 Sep 2020 | | Contributor(s):: Woojin Choi, Venkatesh Balasubramanian, Peter M. Asbeck, Shadi Dayeh
The concept of an intrinsically synthesizable linear device is demonstrated. It was implemented by changing only the device layout; additional performance gains can be attained by further materials engineering.