Tags: nanotransistors

Description

A nanotransistor is a transistor whose dimensions are measured in nanometers. Transistors are used for switching and amplifying electronic signals. When combined in the millions and billions, they can be used to create sophisticated programmable information processors.

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  1. Schottky-Barrier CNFET

    16 Mar 2007 | | Contributor(s):: Arash Hazeghi, Tejas K, H.-S. Philip Wong

    Simulate Carbon Nanotube field Effect transistor with Schottky Barriers

  2. QuaMC2D

    13 Mar 2006 | | Contributor(s):: Shaikh S. Ahmed, Dragica Vasileska

    Quantum-corrected Monte-Carlo electron transport simulator for two-dimensional MOSFET devices.

  3. Nano-CMOS

    06 Feb 2007 | | Contributor(s):: wei zhao, yu cao

    Predictive model files for future transistor technologies.

  4. ECE 612 Lecture 27: RF CMOS

    23 Jan 2007 | | Contributor(s):: Mark Lundstrom

  5. ECE 612 Lecture 30: UTB SOI Electrostatics

    08 Jan 2007 | | Contributor(s):: Mark Lundstrom

  6. ECE 612 Lecture 26: CMOS Limits

    08 Jan 2007 | | Contributor(s):: Mark Lundstrom

  7. ECE 612 Lecture 22: CMOS Process Steps

    04 Jan 2007 | | Contributor(s):: Mark Lundstrom

  8. ECE 612 Lecture 34: Heterostructure FETs

    04 Jan 2007 | | Contributor(s):: Mark Lundstrom

  9. ECE 612 Lecture 33: Heterojunction Bipolar Transistors

    11 Dec 2006 | | Contributor(s):: Mark Lundstrom

  10. ECE 612 Lecture 32: Heterojunction Diodes

    08 Dec 2006 | | Contributor(s):: Mark Lundstrom

  11. ECE 612 Lecture 31: Heterostructure Fundamentals

    08 Dec 2006 | | Contributor(s):: Mark Lundstrom

  12. ECE 612 Lecture 29: SOI Electrostatics

    04 Dec 2006 | | Contributor(s):: Mark Lundstrom

  13. ECE 612 Lecture 28: Overview of SOI Technology

    30 Nov 2006 | | Contributor(s):: Mark Lundstrom

  14. Design in the Nanometer Regime: Process Variation

    28 Nov 2006 | | Contributor(s):: Kaushik Roy

    Scaling of technology over the last few decades has produced an exponential growth in computing power of integrated circuits and an unprecedented number of transistors integrated into a single. However, scaling is facing several problems — severe short channel effects, exponential increase in...

  15. Design of CMOS Circuits in the Nanometer Regime: Leakage Tolerance

    28 Nov 2006 | | Contributor(s):: Kaushik Roy

    The scaling of technology has produced exponential growth in transistor development and computing power in the last few decades, but scaling still presents several challenges. These two lectures will cover device aware CMOS design to address power, reliability, and process variations in scaled...

  16. MOSCNT: code for carbon nanotube transistor simulation

    14 Nov 2006 | | Contributor(s):: Siyu Koswatta, Jing Guo, Dmitri Nikonov

    Ballistic transport in carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) is simulated using the Non-equilibrium Green’s function formalism. A cylindrical transistor geometry with wrapped-around gate and doped source/drain regions are assumed. It should be noted...

  17. recursive algorithm for NEGF in Matlab

    13 Nov 2006 | | Contributor(s):: Dmitri Nikonov, Siyu Koswatta

    This zip-archive contains two Matlab functions for the recursive solution of the partial matrix inversion and partial 3-matrix multiplication used in the non-equilibrium Green’s function (NEGF) method.recuresealg3d.m- works for 3-diagonal matricesrecuresealgblock3d.m- works for 3-block-diagonal...

  18. ECE 612 Lecture 25: CMOS Circuits, Part I I

    06 Nov 2006 | | Contributor(s):: Mark Lundstrom

  19. ECE 612 Lecture 23: CMOS Process Flow

    06 Nov 2006 | | Contributor(s):: Mark Lundstrom

  20. ECE 612 Lecture 24: CMOS Circuits, Part I

    05 Nov 2006 | | Contributor(s):: Mark Lundstrom