I want to make a compact model for FinFET with Verilog-A to use it in HSpice, but I'm really new in this subject and don't know where to start. Can anyone help me with some documents in this subject?
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Aniket Balkrishna parab
Cyril J Azariah
Theory and characterization of random defect formation and its implication in variability of nanoscale transistors
30 Sep 2011 | Contributor(s):: Ahmad Ehteshamul Islam
Over the last 50 years, carrier transport has been the central research topic in the semiconductor area. The outcome was a dramatic improvement in the performance of a transistor, which is one of the basic building blocks in almost all the modern electronic devices. However, nanoscale dimensions...
Quantum dot transistor
Designing of quantum dot transistor.(single electron transistor).the source is connected to the drain via quantum dot, which acts as an island. The quantum dot is controlled by gate electrode.my...
Simulator for a T-stub transistor in a magnetic field
12 Mar 2010 | | Contributor(s):: Massimo Macucci
Simulates transport and shot noise in a t-stub transistor in the presence of a magnetic field
2010 MNTL UIUC Symposium Lecture 1 - Milton Feng at 60 : The Metamorphosis of the Transistor into a Laser
23 Jul 2010 | | Contributor(s):: Nick Holonyak, Jr
Lecture 1b: Nanotransistors - A Bottom Up View
19 Jul 2010 | | Contributor(s):: Mark Lundstrom
MOSFET scaling continues to take transistors to smaller and smaller dimensions. Today, the MOSFET is a true nanoelectronic device – one of enormous importance for computing, data storage, and for communications. In this lecture, I will present a simple, physical model for the nanoscale MOSFET...
OMEN Nanowire: First-Time User Guide
21 Feb 2009 | | Contributor(s):: SungGeun Kim, Benjamin P Haley, Mathieu Luisier, Saumitra Raj Mehrotra, Gerhard Klimeck
This is the first-time user guide for OMEN Nanowire. In addition to showing how the tool operates, it briefly explains what the OMEN Nanowire is, what it can do, and the input and output relationship.NCN@Purdue Sung Dae Suk, et. al., IEDM, 2005, "High Performance 5nm radius Twin Silicon...