Unimore Resistive Random Access Memory (RRAM) Verilog-A Model
22 May 2019 | Compact Models | Contributor(s):
By Francesco Maria Puglisi1, Tommaso Zanotti1, Paolo Pavan1
Università di Modena e Reggio Emilia
The Unimore RRAM Verilog-A model is a physics-based compact model of bipolar RRAM which includes cycle-to-cycle variability, thermal effects, self-heating, and multilevel Random Telegraph Noise (RTN).
W. S. Grabinski
I want to make a compact model for FinFET with Verilog-A to use it in HSpice, but I'm really new in this subject and don't know where to start. Can anyone help me with some documents in this subject?
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MIT TFET compact model including the impacts of non-idealities
03 May 2017 | Compact Models | Contributor(s):
By Redwan Noor Sajjad1, Ujwal Radhakrishna2, Dimitri Antoniadis1
1. Massachusetts Institute of Technology 2. Massachusetts Institute of Technology (MIT)
We present a compact model for tunnel FET that for the first time fits experimental transfer and output characteristics including the impact of non-idealities such as trap assisted tunneling and...
Flexible Transition Metal Dichalcogenide Field-Effect Transistor (TMDFET) Model
07 Apr 2016 | Compact Models | Contributor(s):
By Morteza Gholipour1, Deming Chen2
1. Babol University of Technology 2. University of Illinois at Urbana-Champaign
Verilog-A model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs), considering effects when scaling the transistor size down to the 16-nm technology node.
Physics-Based Compact Model for Dual-Gate Bilayer Graphene FETs
06 Apr 2016 | Compact Models | Contributor(s):
By Jorge-Daniel Aguirre Morales1, Sébastien Frégonèse2, Chhandak Mukherjee3, Cristell Maneux3, Thomas Zimmer3
1. CNRS, University of Bordeaux, IMS Laboratory 2. CNRS, IMS Laboratory 3. University of Bordeaux, IMS Laboratory
A compact model for simulation of Dual-Gate Bilayer Graphene FETs based on physical equations.
7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations
23 Aug 2013 | Contributor(s):: Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy
This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table model was generated using NEMO5 atomistic...
Introduction to Compact Models and Circuit Simulation
21 Jun 2013 | | Contributor(s):: Jaijeet Roychowdhury
With NEEDS introduction by Mark Lundstrom. This talk contains a brief introduction to Verilog-A and suggests some initial guidelines for writing Verilog-A versions of NEEDS models.