Tags: Verilog-A

Resources (1-4 of 4)

  1. Unimore Resistive Random Access Memory (RRAM) Verilog-A Model

    22 May 2019 | Compact Models | Contributor(s):

    By Francesco Maria Puglisi1, Tommaso Zanotti1, Paolo Pavan1

    Università di Modena e Reggio Emilia

    The Unimore RRAM Verilog-A model is a physics-based compact model of bipolar RRAM which includes cycle-to-cycle variability, thermal effects, self-heating, and multilevel Random Telegraph Noise (RTN).

    http://nanohub.org/publications/289/?v=1

  2. MIT TFET compact model including the impacts of non-idealities

    03 May 2017 | Compact Models | Contributor(s):

    By Redwan Noor Sajjad1, Ujwal Radhakrishna2, Dimitri Antoniadis1

    1. Massachusetts Institute of Technology 2. Massachusetts Institute of Technology (MIT)

    We present a compact model for tunnel FET that for the first time fits experimental transfer and output characteristics including the impact of non-idealities such as trap assisted tunneling and...

    http://nanohub.org/publications/181/?v=1

  3. Flexible Transition Metal Dichalcogenide Field-Effect Transistor (TMDFET) Model

    07 Apr 2016 | Compact Models | Contributor(s):

    By Morteza Gholipour1, Deming Chen2

    1. Babol University of Technology 2. University of Illinois at Urbana-Champaign

    Verilog-A model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs), considering effects when scaling the transistor size down to the 16-nm technology node.

    http://nanohub.org/publications/134/?v=1

  4. Physics-Based Compact Model for Dual-Gate Bilayer Graphene FETs

    06 Apr 2016 | Compact Models | Contributor(s):

    By Jorge-Daniel Aguirre Morales1, Sébastien Frégonèse2, Chhandak Mukherjee3, Cristell Maneux3, Thomas Zimmer3

    1. CNRS, University of Bordeaux, IMS Laboratory 2. CNRS, IMS Laboratory 3. University of Bordeaux, IMS Laboratory

    A compact model for simulation of Dual-Gate Bilayer Graphene FETs based on physical equations.

    http://nanohub.org/publications/133/?v=1