Tags: Verilog-A

All Categories (1-7 of 7)

  1. I want to make a compact model for FinFET with Verilog-A to use it in HSpice, but I'm really new in this subject and don't know where to start. Can anyone help me with some documents in this subject?

    Closed | Responses: 0

    http://nanohub.org/answers/question/1942

  2. MIT TFET compact model including the impacts of non-idealities

    03 May 2017 | Compact Models | Contributor(s):

    By Redwan Noor Sajjad1, Ujwal Radhakrishna2, Dimitri Antoniadis1

    1. Massachusetts Institute of Technology 2. Massachusetts Institute of Technology (MIT)

    We present a physics based compact model for Tunnel Field Effect Transistor (TFET), MIT TFET compact model, that captures the device physics of TFETs including non-idealities such as the interface...

    http://nanohub.org/publications/181/?v=1

  3. Flexible Transition Metal Dichalcogenide Field-Effect Transistor (TMDFET) Model

    07 Apr 2016 | Compact Models | Contributor(s):

    By Morteza Gholipour1, Deming Chen2

    1. Babol University of Technology 2. University of Illinois at Urbana-Champaign

    Verilog-A model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs), considering effects when scaling the transistor size down to the 16-nm technology node. This model...

    http://nanohub.org/publications/134/?v=1

  4. Physics-Based Compact Model for Dual-Gate Bilayer Graphene FETs

    06 Apr 2016 | Compact Models | Contributor(s):

    By Jorge-Daniel Aguirre Morales1, Sébastien Frégonèse2, Chhandak Mukherjee3, Cristell Maneux3, Thomas Zimmer3

    1. CNRS, University of Bordeaux, IMS Laboratory 2. CNRS, IMS Laboratory 3. University of Bordeaux, IMS Laboratory

    A compact model for simulation of Dual-Gate Bilayer Graphene FETs based on physical equations.

    http://nanohub.org/publications/133/?v=1

  5. Ozgur Polat

    http://nanohub.org/members/104542

  6. 7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations

    23 Aug 2013 | Downloads | Contributor(s): Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy

    This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations....

    http://nanohub.org/resources/19195

  7. Introduction to Compact Models and Circuit Simulation

    21 Jun 2013 | Online Presentations | Contributor(s): Jaijeet Roychowdhury

    With NEEDS introduction by Mark Lundstrom. This talk contains a brief introduction to Verilog-A and suggests some initial guidelines for writing Verilog-A versions of NEEDS models.

    http://nanohub.org/resources/18678