Tags: Verilog-A

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  1. Physics-Based Compact Model for Dual-Gate Bilayer Graphene FETs

    06 Apr 2016 | Compact Models | Contributor(s):

    By Jorge-Daniel Aguirre Morales1, Sébastien Frégonèse2, Chhandak Mukherjee3, Cristell Maneux3, Thomas Zimmer3

    1. CNRS, University of Bordeaux, IMS Laboratory 2. CNRS, IMS Laboratory 3. University of Bordeaux, IMS Laboratory

    A compact model for simulation of Dual-Gate Bilayer Graphene FETs based on physical equations.

    http://nanohub.org/publications/133/?v=1

  2. Ozgur Polat

    http://nanohub.org/members/104542

  3. 7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations

    23 Aug 2013 | Downloads | Contributor(s): Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy

    This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations....

    http://nanohub.org/resources/19195

  4. Introduction to Compact Models and Circuit Simulation

    21 Jun 2013 | Online Presentations | Contributor(s): Jaijeet Roychowdhury

    With NEEDS introduction by Mark Lundstrom. This talk contains a brief introduction to Verilog-A and suggests some initial guidelines for writing Verilog-A versions of NEEDS models.

    http://nanohub.org/resources/18678