W. S. Grabinski
I want to make a compact model for FinFET with Verilog-A to use it in HSpice, but I'm really new in this subject and don't know where to start. Can anyone help me with some documents in this subject?
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7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations
23 Aug 2013 | Contributor(s):: Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy
This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table model was generated using NEMO5 atomistic...
Introduction to Compact Models and Circuit Simulation
21 Jun 2013 | | Contributor(s):: Jaijeet Roychowdhury
With NEEDS introduction by Mark Lundstrom. This talk contains a brief introduction to Verilog-A and suggests some initial guidelines for writing Verilog-A versions of NEEDS models.