p-bits for Probabilistic Spin Logic (PSL)

by Joseph M. Cychosz, Kerem Yunus Camsari, Lakshmi Anirudh Ghantasala, Supriyo Datta

Nanomagnets used in memory and logic usually have a large barrier ~40-60kT and require relatively large currents to switch, which limits their practical application. Magnets with smaller barriers would require smaller currents and hence less power, but the practical utility of such magnets has been limited since they do not have a stable magnetization and cannot represent a 0 or a 1. Such stochastic nanomagnets (SNM) having thermal stabilities of only a few kT, comprising a few thousand spins, provide natural probablistic bits or "p-bits" for implementing a new kind of logic. The natural physics of SNMs mimic the mathematics of Boltzmann Machines, and can provide the basis for a probabilistic spin logic for a wide variety of low power computing applications.

Links

  • A simulation tool that allows users to play around with various p-bit architectures can be found here (developed by Brian Sutton).
  • Research conducted by Dr. Datta's group is part of a larger effort by CAPSL to investigate the usefulness of probabilistic bits. 
  • Dr. Datta's personal website can be found here.

The following 2-part, 60 minute lecture by Dr. Datta explains the origins and uses of p-bits in greater detail. 

Part 1

Part 2

P-bits

Stochastic p-bits for Invertible Logic, Camsari et. al. (2017)

The behavior of a p-bit can be naturally reproduced with a low kT nanomagnet implanted into an MTJ. The terminal Vout will tend towards 0, 1, or neither based on the voltage on Vin. This behavior is expressed in the graphs above. 

P-bits can be connected in a specific way to form a network which, based on edge weights, can be used to solve the problems hinted at above. These connections are dictated by two simple equations.

    1. mi(t) = sgn{rand(−1,1) + tanh(Ii(t))}

    2. Ii(t) = I0{hi+∑Jijmj(t)}

Simply put, the input to a p-bit is the summation of the outputs of every p-bit connected to it, multiplied by the weights of their connection. The output of a p-bit is a random m (1,-1), either made to output a 1 with a higher probability or lower probability based on the input. A higher input leads to a higher probability of outputting a 1, and vice versa. These equations describe a powerful, versatile system that not only solve a wide array of problems, but lend to that solution the benefit of invertibility.

Boltzmann Machines

And Gate

Pbits are a prime candidate for building Boltzmann Machines. Boolean logic gates, such as and gates and or gates, are Boltzmann machines that take advantage of the invertible nature of pbit networks. Just as pinning the inputs to an AND gate at 1 will produce a 1 at the output, pinning the output at 1 will produce 1s on the inputs. An and gate takes 3 pbits (FIND IMAGE). Its' behavior closely resembles what boltzmann statistics predict. 

Hardware emulation of stochastic p-bits for Invertible logic, Zeeshan et. al. (2017)

A B and C are the three terminals of an AND gate, such that A&B = C. The 4 states occupied with highest probability are the 4 possible states for an AND gate. If no terminals are pinned, PSL can be used to generate a truth table for the given gate, or collection of gates. 

Subset Sum

Subset sum is a popular NP-Complete computer science problem that asks whether or not some subset S' within a set G of positive numbers sum to a specified target. This problem can be represented via PSL in a network of p-bits that form a 2 layer N-bit adder. The first layer sums two numbers while the second one adds to that sum a third number. This architecture makes use of PSL's invertibility feature, allowing us to pin the output sum bits of the full adders, while the inputs fluctuate to the correct addends. The set G is limited, however, to numbers that result from certain bit flips. 

Optimization

An array of pbits can be used for forming a larger network that can be used for combinatorial optimization problems.

Travelling Salesman Problem          

  

Satellite imagery courtesy of Google and TerraMetrics, 2017

The TSP is a famous computer science problem in which one must find the optimal path a salesman would take as they travel from city to city. Namely, the goal is to find a minimum length closed path that visits every node in a graph exactly once. By arranging a network of pbits, and limiting weights based on the constraints of the problem, PSL solves this problem. The nontrivial nature of the problem proves the versatility of PSL. More information regarding solving the TSP with PSL can be found at the following tool, which also simulates solving a 6-city problem: https://nanohub.org/resources/pslsim (developed by Brian Sutton).

 

Bayesian Networks

                Rain, Cloud, pond?

Hardware Implementations

CMOS

Arduino

PSL has been implemented via a network of interconnected arduino mini's, in which each arduino mini represents a single p-bit. This network shed light on what issues arise when PSL is translated into hardware that makes use of real voltages and currents to represent information. 

FPGA

FPGA's form a natural hardware housing for PSL in that they are highly parallel by nature. Though AND-gates and full adders are dense networks, and must be updated sequentially, these boltzmann machines can be run in parallel when they are connected to form n-bit composite machines. Parallel computation, paired with a novel implementation of a "weighted p-bit", a unit that not only includes the neuron but the weights connected to it, have made the FPGA an efficient hardware test-chamber for PSL networks. 

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