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Prashanth Dhundra

How to define source and drain region for 3D cylindrical VNAND flash memory cell structure

Hi,

Can anybody help me in creating source/drain region if I want to create a 3D cylindrical SONOS memory using Sentaurus Structure Editor? I can give more details based on your query.

Thank you.

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    Anonymous

    I don't know anything about Sentaurus. 

    But if you want to model a single cell from a 3D structure, I might be able to help generally.

    All 3D NAND to date has a GAA structure around some sort of vertical tube. The problem with a vertical channel is that it is impossible to create defined implants into such as device; there is no such thing as vertical lithography. Therefore, the tubes that contain the channels for all of the memory cells can either be undoped, or co-doped at time of deposition. The latter method is the case for VNAND. 

    Source and drain regions are required for transistors to function, at least in the classical sense. Since there is only one doping level for the entire polysilicon tube, you may ask, where are the source and drain regions for each memory transistor in VNAND then? 

    The answer to your question really has two parts. The first part is the answer to the above question about source/drain locations for each memory transistor. This requires a different type of FET: a fringing field effect transistor, or so-called "junctionless" transistor. Each transistor in the array, taken individually without considering the ends of the poly tubes, can essentially work like one of those.The second part of the answer just became obvious: The actual source/drains are at the ends of the poly tubes. The heavily co-doped poly plug at the top, and the implanted region in the substrate beneath the GST. 

    So, you could model your individual GAA memory cell in two ways, one as a JT, or one with displaced s/d regions. The truth lies somewhere in between.  

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