nanoHUB-U Fundamentals of Nanotransistors/Lecture1.4: Transistors to Circuits
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[Slide 1] So hello again. We're in the middle of Unit 1 and in Lecture 4. What we're going to do is to take a little detour in the course. We're going to talk about circuits. That's not the main focus of the course. But transistors are used in circuits. Transistor performance determines the performance of circuits. So we need to understand a little bit about how transistor performance relates to circuit performance and then we'll focus on the transistor itself for the rest of this course.
[Slide Change Tone] So in the last lecture, we talked about various device metrics like ION and IOFF and device parameters like threshold voltage and VDSAT, things like that. The question for this lecture is how do these parameters and device metrics affect the performance of real circuits.
[Slide 2] So remember, we have two flavors of transistors. We have N-channel MOSFETs. We draw the circuit schematics this way. If we have a gate and we have a drain and we have a source, we might have a body contact too, depending on the particular flavor of transistors. If we apply gate voltage greater than the threshold voltage, we turn the transistor on and then we apply a positive voltage between the drain and the source. And we get output characteristics that look like these family of I-V characteristics for different gate voltages. This is an n-MOS device, N-channel MOS transistor.
[Slide 4] Now we have complementary technology. So every time we have N-channel device, we have a P-channel device. And in the P-channel device, we have a little circle here so that we can remember that this is a P-channel device. In a P-channel device, all the currents flow in the opposite direction. We apply voltages of the opposite sign. So the threshold voltage is actually a negative quantity. We have to apply a gate voltage that is more negative than the threshold voltage to turn the P-channel transistor on. And we apply a negative voltage between the drain and the source. So the I-V characteristics get flipped around, but they look very similar. So we have both N-channel devices and P-channel devices.
[Slide 5] Now the basic building block for a digital integrated circuit is the CMOS inverter. There's an N-channel device and P-channel device and you can see it here. So down on the bottom, this is our N-channel transistor. The input signal is attached to the gate of the NMOS. Here's the drain, which is attached to the output of this inverter. And the source is grounded. Now up on top-- Well, just to clarify here, the gate-to-source voltage, which controls the performance of the NMOS device, this is just the input voltage of this circuit. Okay, then up on top, we have a PMOS transistor, but it's very important to recognize that this device is hooked up upside down. The source is on top. The power supply, maybe one volt, is up here. The drain is on the bottom and it's connected to the output. So the two drains of the NMOS and PMOS are connected together and the gate is connected to the same input that the gate of the NMOS was. Now if you look here, what's important always in a transistor is the voltage between the gate and the source. That's what determines whether we're on or off. And that gate-to-source voltage in the PMOS is the input voltage minus the voltage on the source, which is the power supply voltage. So the input voltage is always between zero and the power supply voltage. So this voltage is always some negative voltage, which is what it needs to be for a PMOS transistor. So that's our basic circuit. The simple way to think about this is it's like two switches that are either on or off, depending on the input voltage compared to the threshold voltage. So we've got an NMOS on the bottom with the switch that's open or closed and we have a PMOS on the top. If we have a low voltage at the input, that gives us a very large negative voltage between the gate and the source of the PMOS. We have very large negative voltage, flips a switch, the PMOS transistor is on. If we have a high voltage on the gate, then we have no voltage difference between the gate and the source of the PMOS. That's off. The switch is open. But a high voltage on the NMOS device flips the transistor on and that switch is flipped and the device is on. The output is connected the ground. So, you know, that basic idea
[Slide 6] we can understand some characteristics about how this device works. So we might be interested in the transfer characteristic. Transfer characteristic is a plot of the output voltage versus the input voltage. So let's say I have a low-input voltage. If I have a low-input voltage, the NMOS device is off. There's nothing connected there. The PMOS voltage, the transistor has a very large negative voltage between its gate and its source. It's on. So the output node is connected to the power supply and the output is high. Low input, high output. It's an inverter. If I connect a high-input voltage to the input terminal, I turn the NMOS on and I connect the output to ground, zero voltage. So now the output is zero. And at the same time, the high voltage here means there's no voltage between the gate and the source of the PMOS. So that switch is open. So we get a transfer characteristic that looks like this. Low input voltage gives us high output voltage. High input voltage gives us a zero output voltage. That's the characteristic of an ideal inverter.
[Slide 7] Now by understanding that, we can understand how you build logic gates, things like NAND gates or NOR gates from which you can do all of digital logic. So you may remember Boolean logic. We have these various functions like and. The AND function, we get a one on the output any time both input A and the input B are a one or a high voltage. If any one of them is zero, we get a zero for the output. It turns out it's easier for us to build NOT-AND gates or NAND gates. So if you look at this particular circuit, it implements a NAND function. And if I look at a particular set of inputs here, let's say I have a one on input A, a zero on input B, and let's figure out why the output is a one in this NOT-AND gate. So if I put a zero on input B, that low voltage means we've open circuited the NMOS transistor N2. So we don't have a connection to ground. That means with that open switch there, the output node is not connected to ground. So it's not zero volts. Let's see what is. If we trace this circuit around, this low voltage on the input signal goes over to the gate of the PMOS transistor P2. A low voltage on the gate and a high voltage on the source give us a very large negative voltage on the PMOS transistor. That flips a switch. The PMOS transistor is on. We connect the output node then to the power supply and we get a one that's out. Now you can trace through what's happening here on input A when we put a one in there and you'll see that it doesn't disturb anything. It doesn't try to connect this anywhere else. So we've implemented this particular function. So with simple ideas like that, we can understand how these logic gates are produced from basic NMOS, PMOS inverters.
[Slide 8] And we can then focus just on the inverter itself and see if we can understand what controls its performance and how does it relate to the device performance. So here's our inverter again. Here's our transfer characteristic. If you plot an actual transfer characteristic, it won't abruptly switch from high to low. It'll do so, hopefully, very sharply over a narrow input range of voltage. So low voltages, we get a high output. High voltages, we get a low output. High-input voltages give us a low-output voltage and the transition between high and low occurs in a very sharp window range.
[Slide 9] Now if we want to compute that characteristic, how would we do that? Well, we would start with our NMOS device and let me plot-- Instead of VDS, I'll plot V out here, because V out, remember this is the drain-to-source voltage of the NMOS transistor. And the input voltage is the gate-to-source voltage of the NMOS. So these are just the output characteristics of the NMOS transistor labeled with the terminals from the CMOS inverter.
[Slide 10] How about the PMOS device? I'll plot it versus the output voltage too. Now remember the source of the PMOS transistor is connected to VDD, the power supply. So when the output is VDD, there is no voltage across the drain to source, it's zero voltage. And when there is zero volts on the output, then there is a very large negative voltage across the drain and the source of the PMOS. So the transistor characteristic gets flipped. It gets flipped along the horizontal axis and it looks like this. When I apply zero volts to the input, remember I have a large voltage on the source, so up here I have a large negative voltage on my PMOS transistor. I get a lot of current. And then the higher the input voltage goes, the smaller the difference in voltage between the gate and the source until I turn the transistor off. So those are my NMOS and PMOS transistors. These two transistors are connected in series. So that means that the two currents have to be equal in this circuit.
[Slide 11] So let me plot them on the same axes and let's see if we can figure out how this inverter works. Okay, so let's first of all pick input voltage zero. So input voltage zero means the PMOS transistor is biased up here on this high current regime. Input voltage zero means the NMOS is off. It's below threshold. Those two curves intersect right there at 0.1. Okay, now let's look at 2/10 of a volt. At 2/10 of a volt, I still have a lot of current on the PMOS. At 2/10 of a volt, I'm beginning to get some current on the NMOS. Those two curves intersect right there at 0.2. At 0.4 volts, you know, now I have only half the current in the PMOS device. I'm starting to get sizable current in the NMOS. The two curves intersect right there. And if I'm looking, my output voltage is still high. You know, these three cases, one, two and three, I've had smallish input voltages. I've got a very high output voltage. But now something happens. If we go to 0.6 volts on the input, now I'm getting a significant current on the NMOS. I'm getting a significantly smaller current on the PMOS. Now the two curves suddenly intersect over here. Now my output voltage has switched very quickly from a large value to a small value. I've gone from a one to a zero on the output and that happens very quickly when these output characteristics are very flat, when we have a high output resistance. And now you can just continue it and we will continue to find the intersections. And as we have higher and higher voltages, we'll just get closer and closer to the power supply voltage. So by doing that graphically or algebraically on a computer,
[Slide 12] we can sketch out these transfer characteristics and we'll get characteristics like this red line. It'll be smooth. Hopefully, it makes an abrupt transition between high and low and then we have a good inverter. But now the important point is you can look through at every one of these points and what you'll find is that if you have a low input and high output, one of the two transistors is turned off. And if you have a high input and a low output, the other transistor is turned off. The only time both transistors are turned on and current is flowing and power is being dissipated is when you're in the process of switching from high to low or low to high. So when we either have a Vin of zero or a V in of one, no current flows. There is no static power dissipation except for leakage currents. So that's what makes the circuit so remarkable. When it's just sitting there doing nothing, not doing any computation, it's not consuming power. Now in practice, there's going to be a little bit of power. There's going to be some leakage current. We saw this in IOFF of one of the device metrics. Now years ago, that was so small, we ignored it. Now that we have billions and billions of transistors on a chip, you know, these small leakage currents and power dissipations add up, so it's become an important thing. So an important device metric is to make sure that when the switches are off, there's as little leakage current flowing as possible. We want a small IOFF.
[Slide 13] Now let's look again at this transfer characteristic. You'll notice that there is a region when the input voltage is low that the output voltage stays high. The input voltage doesn't have to be precisely zero as long as it's just low enough, I'll get a high enough output voltage and that'll be a logic one. Same thing on the high end, as long as the input voltage is high enough, I get a voltage that's small. So that's a very nice property of this circuit and I can quantify that by looking at the region where the slope becomes steep. So I look at the point where the magnitude of the slope is one, slope is minus one at both the low end and the high end. And I'll define those two regions as my noise margin. So noise margin low means any input voltage doesn't have to be exactly zero. It can be a small number. But as long as it's smaller than noise margin low, we'll get a high output and we'll interpret that as a digital one. Same thing on the high end, there's a noise margin on high as long as the input voltage is high enough, I'll get a small output that we interpret as a logic zero. So this is a very, very useful property of the circuit because it means that there's noise or if things aren't exactly right, the inverter will restore the output voltage to its proper level.
[Slide 14] So we can't make digital circuits with billions of transistors without that property, because otherwise the errors will just add up. They don't add up. They get reset all of the time to their appropriate values. And you can see what would happen, you know, we want a sharp transition between the high output and the low output. The steepness of that slope is something that we call the gain of the inverter, A sub v. It's the change in the output voltage with respect to the change in the input voltage. If we were making an analog amplifier, we would have a little input voltage that we would send in, maybe an AC signal, and this gain then would amplify it and we would get a big voltage out. We'd want a high gain. But gain is also important in digital circuits and you can see why. If the slope of this line was minus 1, then there would be no region on the low end or the high end where the output is insensitive to the precise value of the input. We wouldn't have any noise margin. Errors would accumulate. We couldn't do digital logic on billions of transistors. So an important requirement of any digital circuit is that we must have noise margins, so that means we must have gain in the transistor. Gain is just delta Vout divided by delta Vin. I can use my chain rule from calculus and I can write that as d(Vout)/d(Ids) times d(Ids)/d(Vin). Now if you look at that, the first term, that's what we call the output resistance of the transistor. That's just the slope of the IV characteristic in the output regime. If you look at the second term, that's the change in drain current for a change in input voltage. That's what we call the transconductance. So an important point is that the gain is transconductance times output resistance and that number must be big enough to give us big enough noise margins. We need-- Transconductance is an important device metric. Output resistance is an important device metric,
[Slide 15] because the two together give us noise margins on our circuit. Okay, so here's our CMOS inverter and we have two transistors. The PMOS is often called the pull-up transistor because when switched on it, it pulls the output up to the power supply voltage. The NMOS transistor is often called the pull-down transistor because when it's turned on, it pulls the output down to ground or V equal zero. And the important points to remember about this circuit is that very little current flows unless we're switching between one and zero. So we have small power dissipation as long as we have low off currents. This circuit displays good noise margins as long as we have adequate gain. So we have adequate gain if we have a good enough transconductance and a large enough output resistance. So the next thing we would like to understand is that when we're switching this device, what controls its speed and what controls its power, because those are important factors for CMOS circuits. So let's have a look at that.
[Slide 16] Let's look at the dynamic performance. So here we have an input signal with a period T that's switching in time between high and low. And we want to see if we can figure out what will happen. So when this signal is low, the PMOS transistor is turned on. We pump charge through the PMOS transistor into the capacitor and the capacitor charges up. Now this capacitor represents everything that this inverter is hooked to. The wires that connect it to other parts of the circuit, the other gates that it's connected to, we lump all of those together into an effective switching capacitance Csw. Now when the input capacitance is or when the input signal is high, then the NMOS turns on and that charge that was stored there is dumped to ground and we go back to zero.
[Slide 17] So we can understand how much power is dissipated in a CMOS circuit if we just look at one half of that. It's the same in the other half. So let's look at the discharge cycle. Let's say we've charged this capacitor up. We remember from basic physics or electrical engineering that when you charge a capacitor up, you stored energy 1/2 CV squared in the capacitor and then you flip the switch and you dump all of that energy to ground and dissipate it and lose it. So at the beginning of the discharge cycle, the energy stored is 1/2 CV squared. At the end of the discharge cycle, the energy stored in the capacitor is zero. Power dissipation is energy divided by time. So power dissipation is CV squared divided by the period. One over the period is the frequency. So we have a simple expression for the power dissipation. Remember, there's almost none when the circuit is not switching, but when it's switching, the power dissipation is proportional to how fast we switch it, how much capacitance we have, and to the square of the voltage in the circuit. This factor alpha, we call this an activity factor. Depending on the circuit, you know, each gate is only switching some small, maybe few percent of the cycles. Does it actually do a switch? It doesn't switch on every cycle. So we want to run this circuit as fast as possible so that we can get as much computation done as possible. And that means that we want the power supply voltage to be as low as possible. So that's something that is important for a device designer. How do we make transistors that operate at very low voltages
[Slide 18] so that we can have low power dissipation? Now the other thing we want to talk about quickly here is speed. What controls the speed of the CMOS circuit? So again, let's think of a switching event. We have an input signal and at time t equal zero, we switch it from low to high. And we ask what happens in the output. Well, if we do that, we're going to turn the NMOS on. Assuming this capacitor was already charged up, we're just going to discharge it. So we'll ask how long does it take to discharge it. That'll be the speed of the circuit. Okay, so we can look at the output voltage and we know that the output voltage was high before we switched. We turn the switch on, we dump all of that charge stored in the capacitor to ground, and the output voltage is going to drop. Now we remember the basic law of a capacitor is current is equal to capacitance times dV/dt. Initially, we have charged the output up to a high voltage. At a high voltage, the NMOS device is operating in the saturation region. So the current is more or less independent of the voltage and that means that this basic equation, I is C dV/dt, tells us that the voltage will just drop linearly with time. That's what happens initially. Finally, the voltage gets so low, the transistor enters the linear region. In the linear region, the transistor is like a resistor. Then we're just discharging a capacitor through a resistor. And you'll remember that that goes as exp(-t/tau) where tau is the RC time constant. So that's what the discharge cycle looks like. We want to estimate how long that takes
[Slide 19] and we can do that very simply. So we start with our basic equation for the capacitor and we say how long does it take to discharge the voltage to half of its initial value. We'll call that the switching time. So we're lucky because during that switching time, the current is almost constant. So if-- In fact, the current is the on current of the transistor, because we've got the maximum voltage on it. So during that time, we can say ION is equal to the switching capacitance times delta V divided by delta t. We're going to reduce the voltage by half of its initial voltage and the time it takes to do that we're going to say is the delay of the circuit or the switching time. So we find that the switching time is 1/2 C times V divided by on current. So important point here, the speed of the circuit is determined by the on current and this is why device designers worry a lot about how do I get as much current as possible at a given power supply voltage, because that will increase the speed of the circuit. Now you might say, well, wait a minute. Doesn't it take some time for the electron to get across the transistor from the source to the drain and yes, it does. That's called the transit time of the transistor. But that time is really very, very short. We're really dominated by the time it takes to put charge into the capacitor and to pull charge out. The actual time it takes an electron go across from the source to the drain is small. So we just assume that we flip the device on. It's got an on current. We flipped it off. It's off. And we evaluate speed based in terms of on current.
[Slide 20] So in summary, the circuit performance is determined by these considerations. The energy that it takes to make a one or a zero is just the energy stored in this capacitor. The dynamic power, or the power while we're switching, is proportional to the activity factor, frequency, capacitance, and voltage squared, that's why voltage is so important. The standby power is just determined by how much leakage there is when the inverter is not switching. The switching delay, the more my on current, the faster the device switches and the faster things operate. And in order to have noise margins so that errors don't accumulate, I have to have gain. And the way I get gain is I make sure I have good transconductance and good output resistance.
[Slide 21] So I'm going to end then just with one, pull it all together with one slot here. And this is something that came from my colleague David Frank at IBM research. And we're going to talk about how we are currently in an era where we would call it the era of power-constrained design. We can, with reasonable cost cooling technologies, remove about 100 watts per square centimeter of heat in a chip. So if you go above that, it gets very complicated. Things get too warm. The cooling technology gets too expensive. So that's our power budget. We can only dissipate 100 watts per square centimeter. Now if we plot this versus integration density, the more transistors I put on, each one has a little bit of off current, so each one has a little bit of power dissipation when it's just sitting there doing nothing, that's what we call the standby power. And if I put too many transistors on a chip, that's going to add up to my entire power budget. And in that case, I can't do any computation or anything useful. So then I put too many transistors on the chip. Now the dynamic power is really the useful power. That's the switching power when I'm doing computation or something useful. If I have a low integration density, then there's none of the standby power. All of my power can go into doing something useful. But if I have a high integration density, I have to make sure that my standby power and my dynamic power add up to my power budget. So I have to be careful. I have to manage the standby power. I have to have low off currents and not too many transistors so that I can use as much dynamic power to do as much as possible. And what's happened in designs these days that if you look at a typical chip, there is a significant fraction of the power is standby power just being dissipated when nothing useful is happening.
[Slide 22] So just to summarize, we understand a little bit now about how circuit performance is related to some of these key device metrics. Now we're going to focus for the rest of the course on what goes on inside these transistors, what determines the magnitude of these device metrics, and how do we make good transistors. So we'll continue then in unit one with a very simple look at how we understand the IV characteristics of a transistor. That'll be the topic for the next lecture.