nanoHUB-U Fundamentals of Nanotransistors/Lecture 2.7: 2D MOS Electrostatics
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[Slide 1] So, it's time to change topics and talk about 2D electrostatics. So, as I mentioned earlier, what we're doing in this unit is talking about some things that are a part of any traditional MOS course. If you've had one, you've talked about most of these topics. But it's really very important to have an understanding of electrostatics because that tells us all about how we move those bands up and down and control the flow of a current. And we need to get a firm understanding of these basic concepts in 1 and 2D electrostatics. And then, we're prepared to appreciate the second half of this course, Units 3 and 4, which are really the unique part, which-- where we talk about how electrons flow across the channel in these very short transistors. So, let's dive into 2D electrostatics. 

[Slide 2] We have been discussing what goes on in the normal direction, assuming that we do not have a source and a drain nearby. OK. But there are also energy band diagrams in that direction, and we have to put the two together really to understand how these devices work, so electrostatics both in the y direction normal to the channel, and in the the x direction along the channel. And you'll remember, in order to draw a two-dimensional energy band diagram, we need a two-dimensional potential profile, psi of x, y. So, we really need to think about how do we solve for that. 

[Slide 3] But before we do that, just to mention, what effect are we trying to explain. What effects do we see in these-- due to these two-dimensional electrostatics? So, for example, here's what we-- some of the things we might see. Here are some transfer characteristics on a log plot for some specific channel length L1. And you can see here, a translation in the horizontal direction as we change the drain voltage so there's some amount of DIBL, right, hopefully not too bad if we have a well-designed transistor. That gives us a change in threshold voltage. Now, let's go for-- to a shorter channel device. If we go to a shorter channel device-- So, one of the things you'll notice is that the threshold voltage is lower, even at low-drain voltage, so that is one 2D effect. Another thing that you'll notice is that when you do a log ID versus VGS plot, you'll see more DIBL. The enhanced DIBL means that 2D electrostatics is even stronger and it's degrading the performance. You might also see here that the subthreshold swing has gotten worse. It takes a larger change in gate voltage to produce the same change in drain current in subthreshold conditions. That's an undesirable effect and that's due to 2D electrostatics as well. Now, if we have a very short channel length, we might have something really drastic happen. We might get a characteristic like that. And a characteristic like that is telling us that current wants to flow all of the time and it really is only weakly dependent on the gate voltage. That is not the kind of transistor that we want. We want the gate voltage to be controlling the current. We would say that that transistor is punched through. So, the takeaways are that DIBL increases. The shorter the channel length, the worse DIBL is. Usually the larger the drain the source voltage is, the worse the DIBL is. The subthreshold swing, it might increase as we decrease the channel length too. If it does, that's undesirable. It might increase as we increase the drain voltage, that's also undesirable. And if we see punchthrough, then we know we're not just dealing with some minor 2D effects that we have to optimize the transistor designed to eliminate, we're dealing-- we're really dealing with some catastrophic 2D effect. 

[Slide 4] So, understanding 2D electrostatics is all about solving the Poisson equation in 2D. So, this is our Poisson equation, relates divergence, displacement field is equal to charge density. Remember that the displacement field is dielectric constant times the electric field. The electric field is minus the gradient of the potential. So, we can get a 2D Poisson equation. And that's the equation that we have to solve. And in general, it's not easy to solve that equation. In fact, it's almost never easy to solve that equation. We're going to avoid solving that equation in this lecture. This lecture is going to be about how do we get some qualitative insight into what the solutions to this equation should look like. At some point if we're doing serious transistor design, we'll actually have to sit down and solve that equation. All right. 

[Slide 5] So, let's look at this in one case, this 2D electron-- you know, what this Poisson equation looks like. We've been doing-- we did the Poisson equation for the 1D MOS capacitor. And below threshold, the charge was only due to ionized acceptors and that was an equation that we could solve. We could solve that 1D Poisson equation in depletion and get analytical results that are very useful. Now, in the 2D MOSFET, even in the depletion approximation, assume that charge is only due to the ionized acceptors, we still get an equation that is pretty complicated to solve and in general is, you know, in general requires some numerical techniques in almost all cases. Now, how do we decide whether we need to solve this 2D equation or not. So, if the band bending in the normal direction is very much stronger than the band bending in the lateral direction, then the first term is negligible compared to the second term and we can go back to solving the 1D equation and we've discussed that earlier. So when that happens, we call it the gradual channel approximation. It means things are happening so slowly and gradually in the lateral direction along the channel that we can assume a 1D solution at any point in the normal direction along that channel. That's more and more difficult to do in modern transistors because channel lengths have been scaled so short. All right, so let's try to understand these things. 

[Slide 6] And maybe the first thing we would understand is earlier we developed an expression for the threshold voltage that involved things like the flat band voltage, the doping of the semiconductor, the oxide capacitance. There was no channel length in our threshold voltage expression. But what you will observe is that if you measure the threshold voltage of MOSFETs that when the channel lengths get very small, the threshold voltage begins to decrease, why is that? Well, it's comes out of a solution to this 2D Poisson equation but let's see if we can intuitively understand why that's occurring. So, here is our 2D Poisson equation. I've just moved the derivative along the channel direction to the other side. OK. Now, if we look at this energy band diagram, so here's one that's computed, this is an energy band profile along the channel. And you will see that the curvature of the conduction band is negative, curves down, but conduction band behaves, goes as minus the potential. That means that the curvature of the potential is positive. That means that the second term here, in this equation, is positive, subtracts from the first term. OK. So if we define something, we'll call-- we'll lump everything on the right-hand side together and we'll call it an effective doping density. It's going to be less than the actual doping density because of the second term there. OK. And if we recognize that it's less and if we go back to our expression that we developed earlier for the threshold voltage, we said it depends on the doping density. Well in reality, it should depend on the effective doping density. And because of two-dimensional electrostatics, the effective doping density is lighter, this term is going to be smaller, the threshold voltage will be reduced. The threshold voltage will be reduced when this curvature is strong enough and that will happen for short channels. So, this explains why the threshold voltage should be expected to drop for short channels and why that VT roll-off is observed. So, that's a qualitative explanation for VT roll-off. 

[Slide 7] Now, what we're going to do is take a number-- we're going to look in a number of different ways at 2D electrostatics avoiding the actual solution of this 2D Poisson equation and see if by looking at it in different ways, we can develop intuition into the solution of this 2D Poisson equation. So the barrier lowering view is another way to develop some intuition. So, this is a conduction band along the source, across the channel and out to drain. OK. We did these kinds of band diagrams before. This is an N region, this is a P region, so there's a built-in potential between the N and the P region, that's VBI. But then if we're drawing this energy band diagram along the surface, the surface potential is pulling the conduction band down. So, this barrier between the source and the channel is the built-in voltage of that PN junction minus the surface potential times Q. OK. Now, if we add a strong drain voltage, we'll pull everything near the drain down. Ideally, we would like to not affect this barrier between the source and the channel. OK. So, if it stays the same, then as we pull the drain voltage down, the drain depletion regions and electric fields penetrate into the channel. But if we designed the transistor well, they won't penetrate in a region near the source and they won't pull down that barrier. So, then we'll say that the barrier height is only controlled by the gate voltage which controls the surface potential, and not at all by the drain voltage. We would say that there is no barrier lowering due to the drain voltage. And since the drained current goes exponentially with the height of that barrier, it's the probability that electrons can hop over that barrier and flow out to the drain. And since the barrier hasn't changed, the current doesn't change and we would expect to have no DIBL. 

[Slide 8] If you measured the IV characteristics, you would get transistor characteristics that look like this. If you look at a specific current and say how much does this characteristic translate in the horizontal direction when I change the drain voltage, it wouldn't translate at all. You would say there's no DIBL. 

[Slide 9] OK. A more realistic case would occur like this. When you pull the drain voltage down, you can see intuitively, you're going to pull everything down. You're going to pull that barrier down a little bit, you know, because the fields from the drain are going to penetrate over here and lower the potential over there. That means there is a little bit of barrier lowering. We'll call that drain-induced barrier lowering. So, now we can see why we named DIBL what we did. It's name after the physical mechanism that is causing this translation. We lower the barrier a little bit, just a little bit delta EB, the current goes exponentially with barrier height. Since the barrier is a little bit lower, the current is a little bit higher and the transistor characteristic has changed. If we look at our IV characteristic, 

[Slide 10] then if we would sit at a particular gate voltage and changed the drain voltage, we would see that the current would increase because the drain voltage now is lowering the barrier and making it easier for current to flow. Normally in DIBL, we look at the horizontal translation but we could look at either the vertical or the horizontal. So, that gives us a nice physical explanation in terms of 2D electrostatics as to what this DIBL is all about, drain-induced barrier lowering. Note, that I still have a good transistor here because the characteristics have just shifted but the subthreshold swing, the slope of those curves in the subthreshold regime has not changed. So there are some 2D electrostatics but it's not yet severe. 

[Slide 11] Now, if things get more severe, if I'm not controlling 2D electrostatics at all, then I might have a well-behaved transistor at a small drain voltage. But if I apply a large drain voltage, then I might get an enormous amount of DIBL. In fact, it might so severe that I get an IV characteristic where it's hard even to define a subthreshold swing. This is what we call punchthrough. And if you look at that characteristic as an output characteristic, this is what punchthrough would look like. So the current is increasing, its control is much by the drain voltage as it is by the gate voltage now and that's undesirable for a transistor. The output resistance is very low, the output conductance is high. 

[Slide 12] So, in thinking about punchthrough, what the physical explanation is sometimes people say that you can think about it because there's a PN junction depletion region around the drain and around the source. And as you increase the drain voltage, the two depletion regions might overlap and then we see say the devices punchthrough. There is a more physical way to look that in terms of energy band diagrams. We always want the energy band diagram to look like this. We want there to be a potential barrier between the source and the drain. Because then if our gate voltage can push that barrier up and down, then our gate has strong control over the current. If I have severe 2D effects and I have-- and I'm punchthrough, my energy band diagram will look like this red dash line. There is no barrier. Current wants to flow now no matter what the gate voltage is. So this loss of this barrier, when that happens, the transistor performance degrades catastrophically and we have a transistor that is punched through. 

[Slide 13] So what we're after is a transistor which in the words of my colleague Dimitri Antoniadis is well-tempered. By well-tempered we mean it is electrostatically well-designed. You know, what is an electrostatically well-designed transistor? It is one in which there is always a barrier between the source and the channel. And the height of that barrier is strongly controlled by the gate voltage and only weakly controlled by the drain voltage. As long as it's weakly affected by the drain voltage, we'll get small amounts of DIBL then we'll get good transistor characteristics. 

[Slide 14] So, to design a short channel transistor and to be well-tempered in this electrostatically well-designed, we have to design the transistor properly to minimize these effects. And how do we do that? Well, that brings us to this important topic of screening. We would like to screen out these electric field lines that are-- that want to penetrate from the drain and go over towards the source under the channel and pull the barrier down. We'd like to screen those out. 

[Slide 15] So, you may remember learning about screening in a basic semiconductor course. If I've got a positive charge in a bulk semiconductor, say one of my dopants, one of my ionized phosphorus atoms, and I have a bunch of mobile electrons in the conduction band, the positive charge is going to attract the negative charge. If I go a ways away, I won't see any net charge. We will say the charge has been screened out. So, the mobile charge moves around whenever it sees a net positive charge. It surrounds it and screens out that net positive charge. So, a little ways away the semiconductor looks neutral. OK. Now, there's some characteristic distance over which that screening occurs and that characteristic distance is related to the number of carriers that are there to move about and do the screening and it's given by this expression which is called that Debye length. So, this is screening in a bulk semiconductor. 

[Slide 16] Now, the type of screening that we have in MOSFETs is a different type of screening. We call it geometric screening. So we have metal plates and we have neutral semiconductors on the bottom. The electric field lines, when I apply a positive voltage on the drain, the electric field lines that emanate from the drain can terminate on negative charges. And they can terminate on a sheet of negative charge on the gate electrode. They can terminate on some charge at the edge of the depletion region in the bulk. And hopefully, they terminate there. And hopefully they don't reach through to the barrier and pull that barrier down. Now, we call this geometric screening. And there's some characteristic screening length there. That's the length over which the electric field lines from the drain are screened out and they're no longer present. So, it's the same type of concept but it depends on the precise 2D geometry of the structure and where the conducted plates or the conductive undepleted parts of the semiconductor reside. 

[Slide 17] OK. This is an example of some calculations of these field lines for a double-gate MOSFET. So, here's our thin silicon layer. Here's our top gate. Here's our bottom gate. You can see the electric field lines emanating from the drain. And you can see that this is a well-designed transistor because most of those electric field lines are screened out. They don't penetrate very deeply over here to the source end of the channel. So, they don't pull the barrier down. So, one of the reasons that people like to use double-gate structures or FinFET structures which are like double gate is that they provide very effective geometric screening, so that the voltage and electric field lines from the drain don't affect what goes on at the beginning of the channel. 

[Slide 18] OK. So, we expect good screening characteristics for double-gate structures. And that's the main reason that the industry has begun to move from these conventional planar MOS structures to these FinFET structures where the silicon channel now is a vertical layer of silicon with a gate electrode that is wrapped around it on both sides. You now have a gate on the top and the bottom. And if we wrap the gate electrode around the channel, we get very effective geometric screening. So, that the electric field lines from the drain have a hard time penetrating through and effecting what happens at the source. 

[Slide 19] So, FinFETS are good for designing electrostatically well-controlled transistors. So, it's important to understand what this screening length is quantitatively. Unfortunately in order to that, you actually have to solve this 2D Poisson equation. So, it depends on the specific geometry of the device, it gets a little bit involved. But the general characteristics are that if you have some screening length in the bulk, you usually get a better screening length for a transistor that is silicon-on-insulator. And if it's a double-gate silicon-on-insulator like ET SOI we discussed, the screening length is even smaller. And if it's a nanowire where you've wrapped the gate completely around the channel totally that's a gate-all-around structure, then the screening length is even shorter. Typically what you'll find is that you have to make the minimum channel length in order to have an electrostatically well-behaved transistor is roughly three of these screening lengths. OK. Now, if you need to get involved in transistor design, you'll want to learn about this. I can point you to a paper that does a solution of this equation for a couple of different devices geometries, so you can see how it is done. It's a very good review article where these authors talk about a variety of the ways that people have attacked this problem in the past. And it's important to know that many of the expressions for screening lengths out there just have a region of validity that is very limited and cannot be used in general. So, if you need to do some serious work on a electrostatic design, be sure to read these papers. 

[Slide 20] So, what we have been doing in this lecture is we've been looking at various ways that we can get some insight into the solution of this 2D Poisson equation without actually solving it. We discussed an effective doping approach where we thought about the effective 2D electrostatics as effectively lowering the doping density in the channel and therefore reducing the threshold voltage. We talked about a barrier lowering view where we talked about how the drain voltage reaches through and lowers the potential barrier between the source and the channel and how that can give us DIBL, lower threshold voltage and even increase subthresholds, swing or catastrophically lead the punchthrough. And we talked about geometric screening length, how we designed transistors in order to minimize these kind of effects. There's another model called the capacitor model which is also useful to know. I don't have time to discuss that here. It's discussed in our lecture notes and I'd encourage you to have a look that as well. 

[Slide 21] So, this was our view of a electrostatically well-designed MOSFET. So, the idea is that the transistor designer designs this MOSFET such that at the top of the barrier where the electric field in the lateral direction is zero 1D MOs electrostatics applies. This simple relation that we developed in the 1D case still holds at that point, a point we call the virtual source. The only difference is that the threshold voltage is weakly dependent on the drain voltage through this DIBL parameter. OK. Now, we also want to have a region near the beginning of a channel where the potential is strongly controlled by the gate voltage and not by the drain voltage. So, the electric field, the lateral electric field along the channel is low there. The value of the potential is mainly controlled by the value of the gate voltage. Now deep in the channel, the potential drops rapidly if we have high-drain voltage. And if we increase the drain voltage even more, we have little effect on the current because most of that increased drain voltage just increases the potential drop here which is not what's limiting the current. What's limiting the current is electrons they need to hop over that barrier. So, if we have a transistor designed this way, it is an electrostatically well-designed or well-tempered MOSFET. 

[Slide 22] And you can see how that works on these numerical simulations. So, here is the conduction band versus position at zero drain voltage and then we increase the drain voltage. You can see initially we produced an electric field, a constant slope in the channel. And then as we increase the drain voltage more, the electric field increases more. But as we keep increasing the electric field, we get to a point where the part of the channel near the source no longer changes. All of the additional voltage drop is occurring near the drain end. So, the current saturates because we're going to see that this is the part of the channel that controls the magnitude of the current. 

[Slide 23] And here is some actual data so that you can see what some of these effects look like on real transistors. This is a transistor from a few years ago with a channel length of 105 nanometers. So, it's electrostatically well-behaved. It has some DIBL but the subthreshold swing is the same under both low-drain voltage and high-drain voltage. But if we look at a shorter channel in the same technology, it has a reasonably good DIBL, degraded a little bit under low-drain voltage. And it has a very bad subthreshold swing under high-drain voltage. This device is almost punchthrough. So, this is a type of-- we want to see a parallel translation of the characteristics. We don't want to see a degradation of the subthreshold slope under high-drain voltage. That's an indication. We have some 2D electrostatic problems that we need to deal with. 

[Slide 24] So just to summarize, 2D MOS electrostatics is bad. It always degrades the device performance. It increases DIBL and it increases the subthreshold swing. The goal of a MOSFET designer, and this is really where a designer would spend most of his or her time is to make the 1D MOS electrostatics we learned in the previous few lectures, hold at this virtual source and to achieve small DIBL and a subthreshold slope parameter m that is close to one. The way to achieve this is to engineer the device such that the gate controls the height of that source to channel barrier and the drain has only a very small influence on that potential. OK. So, that is basically it. We have covered 2D MOS electrostatics which is really a very important part of understanding how MOSFETs work. That's a very important part of the challenge that MOSFET designers face. And in order to, sort of wrap up Unit 2, we want to take this understanding of electrostatics that we have developed in this unit and we want to revisit that virtual source model. And we can very easily now convert our level zero virtual source model into a quite good model for nanotransistors. So, that will be the topic of our discussion in the next lecture.