NEEDS Berkeley Workshop 2016

Modelling using Verilog-A in MAPP: A Hands-On Workshop

8 AM - 6 PM
Thursday, Feb 4, 2016

University of California, Berkeley
Hughes Room, 400 Cory Hall
Berkeley, CA 94720

Berkeley's Model and Algorithm Prototyping Platform (MAPP) is a MATLAB-based platform that provides a complete environment for developing, testing, experimentally validating, and inserting compact models in open source simulation platforms. It is also useful for prototyping new simulation algorithms.

This hands-on workshop will focus on the newly developed Verilog-A to ModSpec device model translator for MAPP, dubbed VAPP (Verilog-A Parser and Processor). The goal of the workshop is to illustrate how VAPP/MAPP facilitates the development of simulation ready compact models. An overview of MAPP's multi-physics modelling and simulation capabilities will also be provided. A hands-on refresher on MAPP will be provided for those who have no prior experience with it.

Please bring your laptop (running linux, OSX or Windows). It would be very helpful if you already have MATLAB installed and running on your laptop; otherwise you may need to access the hands-on components through the web.

For more information about MAPP, see:

For other questions, please contact Vicki Johnson at

8:00 AM Coffee, juice, and rolls  
8:30 AM Introduction to NEEDS, MAPP and VAPP Mark Lundstrom and Jaijeet Roychowdhury
9:00 AM VAlint/VAPP/MAPP setup
Participants will set up and test VAlint, VAPP and MAPP on their laptops.
Gokcen Mahmutoglu, Xufeng Wang, Tianshi Wang, Archit Gupta, Jaijeet Roychowdhury
9:30 AM Hands on MAPP refresher
The presenter will outline the capabilities and features of MAPP/ModSpec and guide participants in using them to model simple devices and simulate small circuits using MAPP's DC, and transient analyses.
Tianshi Wang
10:15 AM Break  
10:25 AM Hands on MAPP refresher (contd.) Tianshi Wang
12:00 PM Working lunch
During lunch, the presenter will outline and demonstrate MAPP's multi-physics modelling and simulation capabilities, using opto-electronics and spintronics examples.
Tianshi Wang
1:30 PM Hands on tutorial on using VAlint/VAPP/MAPP for device model development.
The presenters will guide participants in using VAlint, VAPP and MAPP to develop/refine simple compact models in Verilog-A: starting with checking the Verilog-A model using VAlint, then translating to ModSpec using VAPP, using MAPP to see characteristic curves, and finally, simulating small circuits using MAPP's DC, AC and transient analyses. Good modelling practices will be discussed and demonstrated.
Gokcen Mahmutoglu and Xufeng Wang
2:45 PM Coffee Break  
3:00 PM VAlint/VAPP/MAPP (contd.) Gokcen Mahmutoglu and Xufeng Wang
4:30 PM Break  
4:45 PM Open QA/discussion session 
- also spillover time if previous activities run over
5:45 PM Wrap up discussion and Q & A  
6:00 PM Adjourn