This talk presents an in depth look at the Verilog-A code for the R3 transistor model. It also includes some general guidelines for writing compact models.
The talk is part of the hands on workshop on developing compact models: How to Write, Develop and Implement a Real Compact Model.
NEEDS: Nano-Engineered Electronic Device Simulation Node is a resource for nanoelectronics supported by the National Science Foundation and the Semiconductor Research Corporation.
Researchers should cite this work as follows:
103 Dicovery Learning Center, Purdue University, West Lafayette, IN