Interconnect, Emerging Logic Switches and Processor Core Energy-Delay Optimization
04 Oct 2017 | Online Presentations | Contributor(s): Chi-Shuen Lee, Saurabh Vinayak Suryavanshi, H.-S. Philip Wong
RRAM Models and Applications to Circuits and Systems
08 Sep 2017 | Online Presentations | Contributor(s): Haitong Li, Zizhen Jiang, H.-S. Philip Wong
Stanford University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model v. 1.0.0
25 Aug 2014 | Compact Models | Contributor(s): Zizhen Jiang, H.-S. Philip Wong
The Stanford University RRAM Model is a SPICE-compatible compact model which describes switching performance for bipolar metal oxide RRAM. In principle, this model has no limitations on the size of the RRAM cell. The complex process of ion and vacancy migration was simplified into the growth of a...
16 Mar 2007 | Tools | Contributor(s): Arash Hazeghi, Tejas Krishnamohan, H.-S. Philip Wong
Simulate Carbon Nanotube field Effect transistor with Schottky Barriers
Resonant Tunneling Diodes: an Exercise
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06 Jan 2006 | Teaching Materials | Contributor(s): H.-S. Philip Wong
This homework assignment was created by H.-S. Philip Wong for EE 218 "Introduction to Nanoelectronics and Nanotechnology" (Stanford University). It includes a couple of simple "warm up" exercises and two design problems, intended to teach students the electronic properties of resonant tunneling...
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Stanford Virtual-Source Carbon Nanotube Field-Effect Transistors Model
08 Apr 2015 | Contributor(s): Chi-Shuen Lee, H.-S. Philip Wong | doi:10.4231/D3BK16Q68
The VSCNFET model captures the dimensional scaling properties and includes parasitic resistance, capacitance, and tunneling leakage currents. The model aims for CNFET technology assessment for the sub-10-nm technology nodes.
30 Mar 2015 | Contributor(s): Chi-Shuen Lee, H.-S. Philip Wong | doi:10.4231/D38W3835S
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