JFETIDG Model for Independent Dual-Gate JFETs 1.0.3

By Colin McAndrew1, Kejun Xia2

1. Freescale Semiconductor 2. NXP Semiconductors

JFETIDG is a compact model for independent dual-gate JFETs. It is also applicable to: resistors with metal shields; the drift region of LDMOS transistors; the collector resistance of vertical bipolar transistors; and junctionless MOS transistors.

Listed in Compact Models

Additional materials available

Version 1.0.3 - published on 27 Jul 2017 doi:10.4231/D3KK94F1N - cite this

Licensed under NEEDS Modified CMC License according to these terms

crossSection.png equivalentCircuit.png


JFETIDG is a compact model for independent dual-gate JFETs. It is applicable to devices with any combination of pn-junction and MOS gates, and is based on an exact solution for the channel conductance integrated along the device length. It includes modeling of the following effects:

  • depletion pinching
  • velocity saturation
  • self-heating
  • channel length modulation (CLM)
  • drain-induced barrier lowering (DIBL)
  • impact ionization
  • mobility modulation
  • parasitic currents, breakdown, and depletion and diffusion charge for pn-junction gates
  • parasitic fixed capacitances for MOS gates
  • local (single device) and global (W and L dependent) geometry models
  • temperature dependence
  • noise
  • statistical variation
  • parameterization in terms of both physical (doping, layer thicknesses, mobility) and phenomenological (depletion pinching, sheet resistance) quantities

Model Release Components ( Show bundle contents ) Bundle

Cite this work

Researchers should cite this work as follows:



This release fixes hidden state issues detected by VALint, includes an improved temperature model that was found necessary to model flapped resistors that have significant self-heating, has updated documentation, and other minor updates and modifications (listed in the release notes and model code).