JFETIDG Model for Independent Dual-Gate JFETs 1.0.3
JFETIDG is a compact model for independent dual-gate JFETs. It is also applicable to: resistors with metal shields; the drift region of LDMOS transistors; the collector resistance of vertical bipolar transistors; and junctionless MOS transistors.
Listed in Compact Models
Additional materials available
Version 1.0.3 - published on 27 Jul 2017 doi:10.4231/D3KK94F1N - cite this
Licensed under NEEDS Modified CMC License according to these terms
Description
JFETIDG is a compact model for independent dual-gate JFETs. It is applicable to devices with any combination of pn-junction and MOS gates, and is based on an exact solution for the channel conductance integrated along the device length. It includes modeling of the following effects:
- depletion pinching
- velocity saturation
- self-heating
- channel length modulation (CLM)
- drain-induced barrier lowering (DIBL)
- impact ionization
- mobility modulation
- parasitic currents, breakdown, and depletion and diffusion charge for pn-junction gates
- parasitic fixed capacitances for MOS gates
- local (single device) and global (W and L dependent) geometry models
- temperature dependence
- noise
- statistical variation
- parameterization in terms of both physical (doping, layer thicknesses, mobility) and phenomenological (depletion pinching, sheet resistance) quantities
Model Release Components ( Show bundle contents ) Bundle
JFETIDG Model for Independent Dual-Gate JFETs 1.0.3 Verilog-A(ZIP | 31 KB)- JFETIDG Model for Independent Dual-Gate JFETs 1.0.3 Benchmarks(ZIP | 664 KB)
JFETIDG Model for Independent Dual-Gate JFETs 1.0.3 Parameters(VAR/WWW/NANOHUB/APP/SITE/PUBLICATIONS/00173/00218/4Y05EKEAJY/PARAMETERS/PARAMETERSETS | 522 B )- JFETIDG Model for Independent Dual-Gate JFETs 1.0.3 Manual(GZ | 170 KB)
2016TED_JFETIDGpartI.pdf(PDF | 2 MB)- 2016TED_JFETIDGpartII.pdf(PDF | 3 MB)
_00_README.txt(TXT | 4 KB)- License terms
Cite this work
Researchers should cite this work as follows:
- Colin McAndrew; Kejun Xia (2017). JFETIDG Model for Independent Dual-Gate JFETs. nanoHUB. doi:10.4231/D3KK94F1N
Tags
Notes
This release fixes hidden state issues detected by VALint, includes an improved temperature model that was found necessary to model flapped resistors that have significant self-heating, has updated documentation, and other minor updates and modifications (listed in the release notes and model code).