This directory contains Verilog-A files for the PSPHV LDMOS model.
Also included are:
- QA tests, test codes, and reference results for the tests
- example model parameter sets for several devices (these
  are used in the QA tests too)
- documentation

PSPHV consists of an enhanced PSP103.6 model for the
core MOS transistor, an updated JFETIDG model for the
drift region, JUNCAP2 for the pn-junction diodes,
and two 3-terminal MOS capacitors based on PSP
for the gate-drain overlap capacitance.

The top level Verilog-A file is: psphv.va
which references macros and analog functions in
PSP103_SPCalculation.include   the core PSP surface potential calculation
PSP103_macrodefs.include       macros used in the PSP core model
general_v1_0_3.va              useful general macros and definitions
jfetidgIds_v1_0_1.va           analog functions used in JFETIDG
junction_v1_0_2.va             analog functions for pn-junction diodes, including JUNCAP2
simulatorFlags.va              some flags to set/unset if there are issues with your compiler
sp_functions.va                analog functions for gate-drain overlap surface potential calculation

Code to run QA tests is in the testCode directory.
The test definitions are in the qaPsphv and shQaSpec
files, these are in the format for the CMC automated
QA procedure. An additional set of tests, derived from
SPHV, are run by the plotQa.py program. Reference
results for all QA tests are in the reference directory.
The script qaRun.sh will automatically run all tests.

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The QA testing is set up to run spectre. In runQa.py (line 13)
simulatorCommand={'spectre': 'PUT THE COMMAND HERE'}
and in testCode/spectre.pm (line 19)
$simulatorCommand="PUT THE COMMAND HERE";
change PUT THE COMMAND HERE to how you invoke spectre on your system.
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The documentation is not yet complete. The papers that describe
PSPHV and JFETIDG are included, as are the user documentation
for PSP, JFETIDG, and JUNCAP2.