As critical transistor dimensions scale below the 100 nm (nanoscale) regime, quantum mechanical effects begin to manifest themselves and affect important device performance metrics. Therefore, simulation tools which can be applied to design nanoscale transistors in the future, require new theory and modeling techniques that capture the physics of quantum transport accurately and efficiently. This thesis outlines a rigorous yet practical approach to model quantum transport in nanoscale silicon transistors based on the non-equilibrium Green's function (NEGF) formalism. The objectives of this thesis are: 1) to implement the appropriate physics and methodology for nanoscale device modeling 2) to develop new TCAD (technology computer aided design) tools for quantum scale device simulation and 3) to examine and assess new features of carrier transport in futuristic nanoscale transistors. Technical issues are investigated by simulating transistors with a silicon-on-insulator (SOI) device geometry, which is widely accepted as the ideal device structure for scaling silicon technology to its fundamental limits. Simulation results presented in this thesis are used to highlight important aspects of carrier transport such as quantum coherence, confinement and tunneling, self-consistent band lineup, the nature of the voltage drop, the role of scattering and the behavior of the current versus voltage characteristics for transistors with differing geometries.
Ramesh Venugopal received his PhD from Purdue University in August 2003.
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Purdue University, West Lafayette, IN