7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations

By Arun Goud Akkala1, Sumeet Kumar Gupta1, Sri Harsha Choday1, Kaushik Roy1

1. Purdue University

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This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table model was generated using NEMO5 atomistic tight binding transport simulator (also available on Nanohub.org).
Usage notes, example input netlists and full device description are also included.

Changelog -

* r2.2 - Updated on 2015/03/30
1. Fixed missing Ifg, Ibg in I(d) and I(s) expressions for non-zero Ifg, Ibg.
2. Changed model folder names to indicate source underlap (su) and drain underlap (du) values
   LUT_Dev1 --> LUT_Sym_su=1.09nm_du=1.09nm
   LUT_Dev2_1 --> LUT_Asym_su=1.09nm_du=1.635nm
   LUT_Dev2_2 --> LUT_Asym_su=1.635nm_du=1.09nm

* r2.1- Updated on 2014/08/11
1. Asymmetric underlap device models have been included under /models/LUT_Dev2_1 & /LUT_Dev2_2.

* r2.0 - Updated on 2013/12/27
1. Direct gate oxide tunneling current is now included. The front and back gate current file data are now non-zero.
2. A substrate capacitance term appears in the Verilog-A code. This has been set to 0.15fF/um.
3. N_FINFET.va and P_FINFET.va have been merged into a single FINFET.va file.
4. With the inclusion of a dummy body contact, both n and p FinFET are now treated as 4 terminal devices. The dummy body contact should always be connected to Source.
5. Only one model, namely LUT_Dev1, is included. Models with varying underlap have been excluded from this package.

* r1.2 - For uniformity, in Dev2_2/, both n and p FinFET models are now for the case with longer underlap on source side. Previously, only n FinFET model had longer underlap on source side and the p FinFET was left to be same as in Dev2_1/
* r1.1 - For the asymmetric underlap device (Dev2), Dev2_1/ contains model data for the case when longer underlap is on drain side and Dev2_2/ contains model data for the case when longer underlap is on source side.


We wish to thank the NEMO5 team for granting us access to the NEMO5 simulator and for providing technical support. This work was funded under the DARPA PERFECT program.

Sponsored by



Tillmann Christoph Kubis; Michael Povolotskyi; Jean Michel D Sellier; James Fonseca; Gerhard Klimeck (2012), "NEMO5 Overview Presentation," https://nanohub.org/resources/14701. HSPICE - http://www.synopsys.com/tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/default.aspx Verilog-A - http://www.accellera.org/downloads/standards/v-ams/VAMS-LRM-2-3-1.pdf


A. A. Goud, S. K. Gupta, S. H. Choday, and K. Roy, "Atomistic Tight-Binding based Evaluation of Impact of Gate Underlap on Source to Drain Tunneling in 5 nm Gate Length Si FinFETs", Device Research Conference Digest, June 2013.

Cite this work

Researchers should cite this work as follows:

  • Arun Goud Akkala, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy (2013), "7nm Si FinFET Models with Symmetric and Asymmetric Underlap for Circuit Simulations," https://nanohub.org/resources/19195.

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