Hot Carrier Degradation Universal Scaling

By Xin Jin

Purdue University

This tool involves discovering the universality of the HCI damage

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Version 1.0 - published on 15 Jan 2015

doi:10.4231/D3804XK98 cite this

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Abstract

This tool is based on a 2008 publication in the Proc. of International Reliability Physics Symposium by Dhanoop Varghese. It involves discovering the universality of HCI damage. Two example Idlin degradation datasets for DeNMOS and DePMOS transistors at various stress drain biases are provided. Degradation curves at various stress drain bias are automatically scaled to form the universal degradation curve. Voltage acceleration factor is calculated from the 1/s vs. Vd plot.

This tool also allows the user to upload their own datasets.

References

Varghese, D., et al. "OFF-state degradation and correlated gate dielectric breakdown in high voltage drain extended transistors: A review." Microelectronics Reliability (2014).

 

Varghese, D., et al. "A comprehensive analysis of off-state stress in drain extended PMOS transistors: Theory and characterization of parametric degradation and dielectric failure." Reliability Physics Symposium, 2008. IRPS 2008. IEEE International. IEEE, 2008.

Cite this work

Researchers should cite this work as follows:

  • Xin Jin (2015), "Hot Carrier Degradation Universal Scaling," https://nanohub.org/resources/hcius. (DOI: 10.4231/D3804XK98).

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