With its rich physical properties, the novel 2-D carbon-based material graphene is expected to play an important role in the advancement of semiconductor technologies. In a recent poll conducted by the International Technology Roadmap for Semiconductors (ITRS), graphene is named as the material most likely to have the greatest impact on geometric scaling. As a two-dimensional material, graphene has a limited phase space for scattering of electrons; hence, the electrons in graphene can have a long mean free path – a property that can be utilized to build a variety of high frequency analog devices and to implement low-power on-chip interconnects. Further, the ambipolar characteristics of graphene allow frequency doubler circuits implemented with a single transistor – something that is not possible with silicon transistors. In my talk, I will examine the requirements and challenges that must be met for graphene electronics, and discuss possible solutions.

In the first part of the talk, I will describe on-chip interconnect applications with single- and multi-layer graphene nanoribbons (GNR). I will present physical models for carrier mobility and per-unit-length resistance for interconnects. The impact of imperfect coupling of contacts with graphene interconnect leads to a non-uniform distribution of current in the graphene multi-layer interconnect structure. I will quantify the limits imposed on the maximum benefit of graphene interconnects due to such imperfect contact coupling and interaction of graphene electrons with the substrate and edge states.

In the second part of the talk, I will present an ambipolar virtual source (AVS) charge-current compact model for nanoscale graphene transistors applicable in radio frequency (RF) circuits. A self-consistent channel-charge- partitioning model valid from drift-diffusive to ballistic transport conditions supplements the transport model. The model has been extensively calibrated with experimental DC I-V and s-parameter measurements of devices with gate lengths from 650 nm to 40 nm. This has allowed the scaling of mobility and virtual source injection velocity of carriers in graphene transistors to be studied for the first time.

I will conclude my talk with opportunities for extending graphene technologies to solar cells, optical modulators, and photo-detectors.

Shaloo Rakheja received the B.Tech. degree in electrical engineering from Indian Institute of Technology, Kanpur, India, in 2005, and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology in 2009 and 2012, respectively. She worked as a Component Engineer at Intel, Bangalore in 2005 and later as an Analog Engineer at Freescale Semiconductor, Noida from 2006 to 2007. She is currently a Postdoctoral Associate with Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge. Over the last five years, she has co-authored twenty-seven international conference and refereed journal publications. She has also co-authored four book chapters and contributed to the chapter on Emerging Interconnects in ITRS 2011. She received the Intel PhD Fellowship for the academic year 2011-2012. She also received the ECE Graduate Research Assistant Excellence Award for the academic year 2011-2012. Her research interests are in alternate state variable devices, non-Boolean and analog-like system architectures, neuromorphic or other biologically-inspired devices, energy harvesting for sensor networks and other mobile devices, and flexible and transparent electronics and optoelectronics for ubiquitous systems.

Nano-Engineered Electronic Device Simulation Node (NEEDS), Network for Computational Nanotechnology, Discovery Park

Researchers should cite this work as follows:

• Shaloo Rakheja (2014), "The Role of Graphene in Semiconductor Technologies," https://nanohub.org/resources/21272.

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