Inter-band Tunnel Transistors: Opportunities and Challenges

By Suman Datta

Electrical Engineering, University of Notre Dame, Notre Dame, IN

Published on

Abstract

Sustaining Moore’s Law over the next decade will require not only continued scaling of the physical dimensions of transistors but also performance improvement and aggressive reduction in power consumption. Several device options beyond FinFETs such as GAA nanowire FETs are being pursued to extend technology scaling beyond 7nm node. Hetero-junction Tunnel FET (HTFET) have emerged as promising transistor candidates for supply voltage scaling down to sub-0.5V due to the possibility of sub-kT/q switching without compromising on-current (ION). Recently n-type III-V HTFET with reasonable on-current and sub-kT/q switching at supply voltage of 0.5V have been experimentally demonstrated. However, steep switching performance of III-V HTFET till date has been limited to range of drain current (IDS) spanning over less than a decade. In this talk, we will review progress in Tunnel FETs and also analyze primary roadblocks in the path towards achieving steep switching performance in III-V HTFET.

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Bio

Suman Datta Suman Datta recently joined the University of Notre Dame as the Chang Family Chair Professor of Engineering Innovation. He was previously a faculty member at Penn State University in Electrical Engineering. He joined Penn State as the inaugural Monkowski Associate Professor in 2007, and was promoted to Full Professor in 2011. Before joining Penn State, from 1999 till 2007, he was in the Advanced Transistor Group at Intel Corporation, where he developed several generations of logic transistor technologies including high-k/metal gate, Tri-gate and alternate channel CMOS transistor technologies. His research interests are in novel solid-state nanoelectronic materials and devices, understanding of transport mechanisms, and ultralow-power circuit applications, with recent emphasis on non-volatile computing powered by energy harvesters and computing using collective state of coupled systems. He was a recipient of the Intel Achievement Award (2003), the Intel Logic Technology Quality Award (2002), the Penn State Engineering Alumni Association (PSEAS) Outstanding Research Award (2012), the SEMI Award for North America (2012), IEEE Device Research Conference Best Paper Award (2010, 2011) and the PSEAS Premier Research Award (2015). He is a Fellow of IEEE.

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Cite this work

Researchers should cite this work as follows:

  • Suman Datta (2015), "Inter-band Tunnel Transistors: Opportunities and Challenges," https://nanohub.org/resources/23000.

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Time

Location

1001 Wang, Purdue University, West Lafayette, IN

Tags

Inter-band Tunnel Transistors: Opportunities and Challenges
  • Inter-band Tunnel Transistors: Opportunities and Challenges 1. Inter-band Tunnel Transistors:… 0
    00:00/00:00
  • Outline 2. Outline 84.818151484818159
    00:00/00:00
  • Computation per kW-hr 3. Computation per kW-hr 211.07774441107776
    00:00/00:00
  • Voltage Scaling 4. Voltage Scaling 291.79179179179181
    00:00/00:00
  • Challenges 5. Challenges 518.38505171838506
    00:00/00:00
  • Si CMOS 6. Si CMOS 777.344010677344
    00:00/00:00
  • Injection Velocity: 22nm Si CMOS 7. Injection Velocity: 22nm Si CM… 854.98832165498834
    00:00/00:00
  • gm vs. SS benchmarking 8. gm vs. SS benchmarking 951.0844177510844
    00:00/00:00
  • Multi-Nanowire GAA: Architectures 9. Multi-Nanowire GAA: Architectu… 1086.252919586253
    00:00/00:00
  • Electron Density Comparison 10. Electron Density Comparison 1215.3820487153821
    00:00/00:00
  • FinFETs vs GAA NWFETs 11. FinFETs vs GAA NWFETs 1283.8505171838506
    00:00/00:00
  • Inter-band Tunnel FET: steep switching FET 12. Inter-band Tunnel FET: steep s… 1363.4634634634635
    00:00/00:00
  • Tunnel FET: steep switching MOSFET alternative 13. Tunnel FET: steep switching MO… 1513.7470804137472
    00:00/00:00
  • P-channel TFET: State of Art 14. P-channel TFET: State of Art 1603.9372706039374
    00:00/00:00
  • P-channel TFET: State of Art 15. P-channel TFET: State of Art 1702.5025025025025
    00:00/00:00
  • N-channel TFET: State of Art 16. N-channel TFET: State of Art 1704.4711378044713
    00:00/00:00
  • N and P-channel HTFET 17. N and P-channel HTFET 1762.862862862863
    00:00/00:00
  • HTFET inverter: Energy Delay Promise 18. HTFET inverter: Energy Delay P… 1927.9279279279281
    00:00/00:00
  • TFET Demonstration Challenges 19. TFET Demonstration Challenges 2017.3840507173841
    00:00/00:00
  • Vertical Tunnel FET 20. Vertical Tunnel FET 2155.5221888555225
    00:00/00:00
  • HTFET Process Flow 21. HTFET Process Flow 2231.1978645311979
    00:00/00:00
  • HTFET Process Flow 22. HTFET Process Flow 2244.2442442442443
    00:00/00:00
  • HTFET Process Flow 23. HTFET Process Flow 2246.6132799466131
    00:00/00:00
  • HTFET Process Flow 24. HTFET Process Flow 2307.2405739072406
    00:00/00:00
  • HTFET Process Flow 25. HTFET Process Flow 2319.9532866199534
    00:00/00:00
  • HTFET Process Flow 26. HTFET Process Flow 2321.6549883216549
    00:00/00:00
  • HTFET: Cross-section TEM 27. HTFET: Cross-section TEM 2324.391057724391
    00:00/00:00
  • PTFET: Gate Stack Optimization 28. PTFET: Gate Stack Optimization 2350.2168835502171
    00:00/00:00
  • PTFET: Gate Stack Optimization 29. PTFET: Gate Stack Optimization 2407.9412746079415
    00:00/00:00
  • NTFET: Gate Stack Optimization 30. NTFET: Gate Stack Optimization 2463.5301968635304
    00:00/00:00
  • NTFET: Gate Stack Optimization 31. NTFET: Gate Stack Optimization 2490.256923590257
    00:00/00:00
  • Optimized Gate Stacks 32. Optimized Gate Stacks 2516.0160160160162
    00:00/00:00
  • P-channel HTFET 33. P-channel HTFET 2527.0603937270603
    00:00/00:00
  • N-channel HTFET 34. N-channel HTFET 2568.7354020687353
    00:00/00:00
  • Output Characteristics 35. Output Characteristics 2597.8311644978312
    00:00/00:00
  • Benchmarking 36. Benchmarking 2664.3309976643309
    00:00/00:00
  • Components of Transport in TFET 37. Components of Transport in TFE… 2796.3630296963634
    00:00/00:00
  • Dit, Tbody (simulation) 38. Dit, Tbody (simulation) 2910.7107107107108
    00:00/00:00
  • Devices to Circuits 39. Devices to Circuits 2941.9085752419087
    00:00/00:00
  • Energy-Delay Comparison 40. Energy-Delay Comparison 2993.5935935935936
    00:00/00:00
  • Hybrid Core Processor 41. Hybrid Core Processor 3030.9642976309642
    00:00/00:00
  • Tunnel FETs for beyond 5nm ? 42. Tunnel FETs for beyond 5nm ? 3032.3323323323325
    00:00/00:00
  • 2D TMD Tunnel FETs 43. 2D TMD Tunnel FETs 3157.223890557224
    00:00/00:00
  • Elastic strain effect on monolayer TMD 44. Elastic strain effect on monol… 3195.895895895896
    00:00/00:00
  • ON-current increases 45. ON-current increases 3243.8104771438107
    00:00/00:00
  • TFET State of the ART 46. TFET State of the ART 3247.5141808475141
    00:00/00:00
  • Take Home Message 47. Take Home Message 3250.9509509509512
    00:00/00:00
  • HTFET: Cross-section TEM 48. HTFET: Cross-section TEM 3383.8505171838506
    00:00/00:00
  • Tunnel FETs for beyond 5nm ? 49. Tunnel FETs for beyond 5nm ? 3832.4657991324661
    00:00/00:00