This is the fifth in a series of talks on device options and trade-offs for the 5 nm node. Negative Capacitor Field Effect Transistors (NC-FETs) promise to sustain Moore’s law by reducing the supply voltage (and thereby, self-heating) below the lowest limit achievable by classical transistors. Conceptually, the reduction in voltage is achieved by integrating a negative capacitor in the gate-stack; the internal voltage amplification turns a transistor on and off at voltages much lower that previously thought possible. Unfortunately, the notion of a “negative capacitor”, the debate regarding experimental demonstrations, apparent disconnect with equations of classical transistors, etc. make the NC-FET a mysterious and hard-to-understand addition to the device literature. In this talk, I use a simple graphical approach to demystify the device and explain why the experimental results are easy to misinterpret. Since the NC-FET is just a special case of a much broader class of phase-change devices and systems (e.g., transistors, memories, MEMS, logic-in-memory architecture) that operate by tailoring the Landau potential energy landscape, once NC-FET is understood, the operation of all other devices becomes intuitively obvious as well. The talk will conclude with a discussion of four possible roads to improving NC-FET device performance.

A MATLAB script that implements the concepts discussed in this tutorial is also available as is a list of resources for Landau switches.

Professor Alam is the Jai N. Gupta Professor of Electrical Engineering at Purdue University where his research focuses on fundamental limits of classical and emerging electronic devices. Before joining Purdue in 2004, Prof. Alam spent a decade in Bell Labs and Agere systems where he made important contributions to reliability physics of transistors and design of optoelectonic integrated circuits. He has published more than 200 papers, presented numerous invited and contributed talks, and more than 100,000 students have learned some aspect of semiconductor devices from his web-based lectures. He is a fellow of IEEE, APS, and AAAS, and recipient of 2006 IEEE Kiyo Tomiyasu Award and 2015 SRC Technical Excellence Award for contributions to device technology for communication systems.

NEEDS: Nano-Engineered Electronic Device Simulation Node, Discovery Park, Network for Computational Nanotechnology

Researchers should cite this work as follows:

• Muhammad A. Alam (2015), "A Tutorial Introduction to Negative-­Capacitor Landau Transistors: Perspectives on the Road Ahead," https://nanohub.org/resources/23157.

  BibTex | EndNote

1. FeFETs
2. ferroelectrics
3. MOSFET
4. nanoelectronics
5. NC-FETs
6. NCN Transistor @ 75
7. NEEDS node
8. negative capacitance