Stochastic Computing for Brainware LSI

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Stochastic computing has been recently studied for soft-error-resilient hardware and approximate computing, such as image processing and machine learning. This talk reviews stochastic computation and discusses the advantages and disadvantages with the recent developments in hardware. In addition, stochastic-computing based brainware LSIs (BLSIs) are introduced.


Naoya Onizawa Naoya Onizawa is an Assistant Professor of the Research Institute of Electrical Communication (RIEC), Tohoku University. He received the B.E., M.E. and D.E. degrees in Electrical and Communication Engineering from Tohoku University, Japan, in 2004, 2006 and 2009, respectively. He is currently an Assistant Professor in Research Institute of Electrical Communication at Tohoku University, and a JST PRESTO researcher, Japan. He was a postdoctoral fellow at University of Waterloo, Canada in 2011 and at McGill University, Canada from 2011 to 2013. In 2015, he was a Visiting Associate Professor at University of Southern Brittany, France. His main interests and activities are in the energy-efficient VLSI design based on asynchronous circuits and probabilistic computation, and their applications, such as brain-like computers.

He received the Best Paper Award in 2010 IEEE ISVLSI, the Best Paper Finalist in 2014 IEEE ASYNC, and Kenneth C. Smith Early Career Award for Microelectronics Research in 2016 IEEE ISMVL. Dr. Onizawa is a Member of the IEEE.

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  • (2020), "Stochastic Computing for Brainware LSI,"

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