47 Electrostatic Engineering in BaTiO3/β-Ga2O3 Heterostructure Field Effect Transistors

By Nidhin Kurian Kalarickal1, Zhanbo Xia1, Wyatt Moore1, Joe McGlone1, Aaron R. Arehart1, Steven A. Ringel2, Siddharth Rajan1

1. Electrical and Computer Engineering, Ohio State University, Columbus, OH 2. Materials Science and Engineering, Ohio State University, Columbus, OH

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Abstract

Day 2 Session 3.3

We report on the design and demonstration of BaTiO3/β-Ga2O3 based lateral field effect transistors with superior breakdown performance. Utilizing the high-k low-k dielectric interface allows significant improvement in electrostatic field management giving a breakdown voltage of 1.1 KV at 5 um and 660 V at 1 um gate-drain distance. This translates to a record power figure of merit (VBR2/RON) of 672 MW/cm2, highest in β-Ga2O3 lateral transistors.

Introduction: The high breakdown field of β-Ga2O3 enables significant improvement in the performance of high voltage switching devices. Together with the availability of bulk substrates, β-Ga2O3 offers a new material platform for future high power switching applications. To date, one of the main factors limiting β-Ga2O3 based devices from achieving near theoretical performance is the lack of a suitable dielectric that can support electric fields in excess of 8 MV/cm and a suitable field management strategy which can enable high average fields. In this report we show that high-k dielectrics (εr > 100) like BaTiO3 can be used as efficient gate dielectrics for β-Ga2O3 since they can enable electric field management by providing high-k low-k dielectric interfaces in both vertical and lateral direction.

Simulation: Fig.1 shows two different designs (design 1, design 2) of a lateral field effect transistor utilizing a highk gate dielectric (εr = 180) and a low-k passivation layer (εr = 5) on top. 2D device simulations using silvaco atlas were used to compare the electric field profile in the both the transistor designs at a high reverse bias of 850 V. As shown in fig.2 transistor design 2 shows much lower peak fields compared to design 1. This is because transistor design 2 offers the advantage of providing a high-k low-k interface not just in the vertical direction but also in the lateral direction. This pushes the peak field from the edge of the gate to the low-k passivation layer. Since the passivation layer can be designed using a high band gap material like SiO2 (8.6 eV), this would enable higher breakdown voltages compared to design 1.

Epitaxial structure: To confirm the simulation results we fabricated lateral field effect transistors similar to design 2. The epitaxial structure of the fabricated device is shown in fig.3. The epilyer was grown using molecular beam epitaxy in a Riber M7 system equipped with an O2 plasma source. The channel layer consits of a 3 nm β-Ga2O3 quantum well with modulation doping (1 nm spacer layer) from either sides of the barrier forming a double barrier heterostructure (DHFET). Si delta doping (2.5 s) was used to dope the barrier layers on either side. HRXRD of the (020) planes was performed post growth showing an Al composition of 17.5 % in the barrier layer. The channel mobility and charge was estimated using hall as 85 cm2/V-s and 9.4 × 1012 cm-2 respectively.

Electrical and breakdown characteristics: Ohmic source and drain contacts were realized by MBE regrowth followed by deposition and annealing (470 ℃ for 1 min) of Ti/Au/Ni ohmic contacts. Transfer length measurements were utilized to estimate a contact resistance of 5.2 Ω.mm. 10 nm of Al2O3 was deposited using ALD and 100 nm of BaTiO3 (670 ℃) was deposited using RF sputtering to form the gate dielectric. The Al2O3 layer was used to avoid sputter damage at the β-Ga2O3 surface. Cr/Pt (5/100 nm) metal stack was then deposited to form the gate. Cr is used to improve the adhesion of Pt on BaTiO3. Following this, PECVD SiO2 (150 nm) is deposited to form the high-k low-k interface in the lateral direction. The final device structure and band diagram is shown in fig. 3 and fig. 4.

Channel mobility and charge density measured post deposition of Al2O3 and 1st layer of BaTiO3 showed no significant changes compared to pre deposition showing that the sputtering process has not affected the transport in the channel. DC I-V and two terminal gate-drain breakdown characteristics were measured to estimate the onresistance
and breakdown voltage (VDG). Fig.5 shows the output characteristics and fig.6 shows the transfer characteristics of a device with a gate-drain spacing of 3 um .The gate-drain distances were confirmed using an SEM. The breakdown voltage was found to increase from 660 V to 1.11 KV as the gate drain spacing is increased from 1 um to 5 um. This corresponds to an average breakdown field of 6.6 MV/cm at 1um and 2.2 MV/cm at 5 um gate drain spacing (fig. 7). The corresponding power figure of merit for the 1 um device is estimated to be 672 MW/cm2 which is the highest reported value for any β-Ga2O3 lateral transistor (fig.8).

In conclusion we have shown that high-k gate dielectrics like BaTiO3 can be used as effective gate-dielectrics
for β-Ga2O3 since they can enable alternate field management strategies unlike low-k gate dielectrics. Utilizing such
strategies we acheived a record power figure of merit of 672 MW/cm2 at a gate-drain spacing of 1 um.

figures

Credits

This work was funded by AFOSR GAME MURI (Grant FA9550-18-1-0479, Program Manager Dr. Ali Sayir).

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Cite this work

Researchers should cite this work as follows:

  • Nidhin Kurian Kalarickal, Zhanbo Xia, Wyatt Moore, Joe McGlone, Aaron R. Arehart, Steven A. Ringel, Siddharth Rajan (2020), "47 Electrostatic Engineering in BaTiO3/β-Ga2O3 Heterostructure Field Effect Transistors," https://nanohub.org/resources/34174.

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DRC 2020 Virtual Conference

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